Datasheet AD9681 (Analog Devices) - 6

Data Sheet AD9681 AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 2. Parameter1 Temp Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz 25°C 74.8 dBFS fIN = 19.7 MHz 25°C 74.7 dBFS fIN = 69.5 MHz Full 72.6 73.9 dBFS fIN = 139.5 MHz 25°C 71.5 dBFS fIN = 201 MHz 25°C 69.6 dBFS fIN = 301 MHz 25°C 66.6 dBFS SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 9.7 MHz 25°C 74.7 dBFS fIN = 19.7 MHz 25°C 74.7 dBFS fIN = 69.5 MHz Full 72.3 73.8 dBFS fIN = 139.5 MHz 25°C 71.4 dBFS fIN = 201 MHz 25°C 69.3 dBFS fIN = 301 MHz 25°C 65.8 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 12.1 Bits fIN = 19.7 MHz 25°C 12.1 Bits fIN = 69.5 MHz Full 11.7 12.0 Bits fIN = 139.5 MHz 25°C 11.6 Bits fIN = 201 MHz 25°C 11.2 Bits fIN = 301 MHz 25°C 10.6 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 94 dBc fIN = 19.7 MHz 25°C 94 dBc fIN = 69.5 MHz Full 81 90 dBc fIN = 139.5 MHz 25°C 87 dBc fIN = 201 MHz 25°C 83 dBc fIN = 301 MHz 25°C 73 dBc WORST HARMONIC (SECOND OR THIRD) fIN = 9.7 MHz 25°C −94 dBc fIN = 19.7 MHz 25°C −94 dBc fIN = 69.5 MHz Full −90 −81 dBc fIN = 139.5 MHz 25°C −87 dBc fIN = 201 MHz 25°C −83 dBc fIN = 301 MHz 25°C −73 dBc WORST OTHER (EXCLUDING SECOND OR THIRD) fIN = 9.7 MHz 25°C −98 dBc fIN = 19.7 MHz 25°C −94 dBc fIN = 69.5 MHz Full −96 −84 dBc fIN = 139.5 MHz 25°C −90 dBc fIN = 201 MHz 25°C −85 dBc fIN = 301 MHz 25°C −75 dBc TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS fIN1 = 70 MHz, fIN2 = 72.5 MHz 25°C 94 dBc CROSSTALK, WORST ADJACENT CHANNEL2 25°C −83 dB Crosstalk, Worst Adjacent Channel Overrange Condition3 25°C −79 dB ANALOG INPUT BANDWIDTH, FULL POWER 25°C 650 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Crosstalk is measured at 70 MHz, with −1.0 dBFS analog input on one channel and no input on the adjacent channel. 3 Overrange condition is defined as 3 dB above input full scale. Rev. C | Page 5 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/OLM Pin SCLK/DTP Pin CSB1 and CSB2 Pins RBIAS1 and RBIAS2 Pins OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel Specific Registers MEMORY MAP MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Enhancement Control (Register 0x0C) Output Mode (Register 0x14) Output Adjust (Register 0x15) Output Phase (Register 0x16) Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) User I/O Control 3 (Register 0x102) APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS BOARD LAYOUT CONSIDERATIONS Sources of Coupling Crosstalk Between Inputs Coupling of Digital Output Switching Noise to Analog Inputs and Clock CLOCK STABILITY CONSIDERATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE