Datasheet AD9653 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | Quad, 16-Bit, 125 MSPS Serial LVDS 1.8 V Analog-to-Digital Converter |
| Pages / Page | 42 / 3 — AD9653. Data Sheet. TABLE OF CONTENTS |
| Revision | F |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
AD9653. Data Sheet. TABLE OF CONTENTS
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AD9653 Data Sheet TABLE OF CONTENTS
Features .. 1 Power Dissipation and Power-Down Mode ... 27 Applications ... 1 Digital Outputs and Timing ... 27 General Description ... 1 Output Test Modes ... 30 Functional Block Diagram .. 1 Serial Port Interface (SPI) .. 31 Product Highlights ... 1 Configuration Using the SPI ... 31 Revision History ... 3 Hardware Interface ... 32 Specifications ... 4 Configuration Without the SPI .. 32 DC Specifications ... 4 SPI Accessible Features .. 32 AC Specifications .. 6 Memory Map .. 33 Digital Specifications ... 8 Reading the Memory Map Register Table ... 33 Switching Specifications .. 9 Memory Map Register Table ... 34 Timing Specifications .. 10 Memory Map Register Descriptions .. 37 Absolute Maximum Ratings .. 12 Applications Information .. 39 Thermal Resistance .. 12 Design Guidelines .. 39 ESD Caution .. 12 Power and Ground Recommendations ... 39 Pin Configuration and Function Descriptions ... 13 Clock Stability Considerations ... 39 Typical Performance Characteristics ... 14 Exposed Pad Thermal Heat Slug Recommendations .. 39 VREF = 1.0 V ... 14 VCM ... 39 VREF = 1.3 V ... 17 Reference Decoupling .. 39 Equivalent Circuits ... 21 SPI Port .. 39 Theory of Operation .. 22 Crosstalk Performance .. 40 Analog Input Considerations .. 22 Outline Dimensions ... 41 Voltage Reference ... 23 Ordering Guide .. 41 Clock Input Considerations .. 25 Rev. E | Page 2 of 41 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.0 V VREF = 1.3 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/OLM Pin SCLK/DTP Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x04, Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Power Mode Clock (Register 0x09) Bits[7:1]—Open Bit 0—Duty Cycle Stabilize Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—1 Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Sample Rate Override (Register 0x100) User Input/Output Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User Input/Output Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT CROSSTALK PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
AD9653 Data Sheet TABLE OF CONTENTS
Features .. 1 Power Dissipation and Power-Down Mode ... 27 Applications ... 1 Digital Outputs and Timing ... 27 General Description ... 1 Output Test Modes ... 30 Functional Block Diagram .. 1 Serial Port Interface (SPI) .. 31 Product Highlights ... 1 Configuration Using the SPI ... 31 Revision History ... 3 Hardware Interface ... 32 Specifications ... 4 Configuration Without the SPI .. 32 DC Specifications ... 4 SPI Accessible Features .. 32 AC Specifications .. 6 Memory Map .. 33 Digital Specifications ... 8 Reading the Memory Map Register Table ... 33 Switching Specifications .. 9 Memory Map Register Table ... 34 Timing Specifications .. 10 Memory Map Register Descriptions .. 37 Absolute Maximum Ratings .. 12 Applications Information .. 39 Thermal Resistance .. 12 Design Guidelines .. 39 ESD Caution .. 12 Power and Ground Recommendations ... 39 Pin Configuration and Function Descriptions ... 13 Clock Stability Considerations ... 39 Typical Performance Characteristics ... 14 Exposed Pad Thermal Heat Slug Recommendations .. 39 VREF = 1.0 V ... 14 VCM ... 39 VREF = 1.3 V ... 17 Reference Decoupling .. 39 Equivalent Circuits ... 21 SPI Port .. 39 Theory of Operation .. 22 Crosstalk Performance .. 40 Analog Input Considerations .. 22 Outline Dimensions ... 41 Voltage Reference ... 23 Ordering Guide .. 41 Clock Input Considerations .. 25 Rev. E | Page 2 of 41 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.0 V VREF = 1.3 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/OLM Pin SCLK/DTP Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x04, Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Power Mode Clock (Register 0x09) Bits[7:1]—Open Bit 0—Duty Cycle Stabilize Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—1 Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Sample Rate Override (Register 0x100) User Input/Output Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User Input/Output Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT CROSSTALK PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
