Datasheet AD9653 (Analog Devices) - 37

AD9653 Data Sheet Default ADDR Bit 7 Bit 0 Value (Hex) Parameter Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments
0x19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User Defined (global) Pattern 1 LSB. 0x1A USER_PATT1_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User Defined (global) Pattern 1 MSB. 0x1B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User Defined (global) Pattern 2 LSB. 0x1C USER_PATT2_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User Defined (global) Pattern 2 MSB. 0x21 Serial output data LVDS SDR/DDR one-lane/two-lane, Open Select Serial output 0x30 Serial stream control (global) output bitwise/bytewise[6:4] 2× number of bits control. LSB 000 = SDR two-lane, bitwise frame 00 = 16 bits Default causes first 001 = SDR two-lane, bytewise MSB first and 010 = DDR two-lane, bitwise the native bit 011 = DDR two-lane, bytewise stream. 100 = DDR one-lane, wordwise 0x22 Serial channel Open Open Open Open Open Open Channel Channel 0x00 Used to status (local) output power- power down reset down individual sections of a converter. 0x100 Sample rate Open Sample 0 0 Open Sample rate 0x00 Sample rate override rate 000 = 20 MSPS override override 001 = 40 MSPS (requires enable 010 = 50 MSPS transfer 011 = 65 MSPS register, 0xFF). 100 = 80 MSPS 101 = 105 MSPS 110 = 125 MSPS 0x101 User Input/Output Open Open Open Open Open Open Open SDIO 0x00 Disables SDIO Control 2 pull- pull-down. down 0x102 User Input/Output Open Open Open Open VCM Open Open Open 0x00 VCM control. Control 3 power- down 0x109 Sync Open Open Open Open Open Open Sync Enable 0x00 next sync only Rev. E | Page 36 of 41 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.0 V VREF = 1.3 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/OLM Pin SCLK/DTP Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x04, Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Power Mode Clock (Register 0x09) Bits[7:1]—Open Bit 0—Duty Cycle Stabilize Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—1 Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Sample Rate Override (Register 0x100) User Input/Output Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User Input/Output Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT CROSSTALK PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE