Datasheet AD9650 (Analog Devices) - 8

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Data Sheet AD9650 SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, and DCS enabled, unless otherwise noted.
Table 4. AD9650BCPZ-25 AD9650BCPZ-65 AD9650BCPZ-80 AD9650BCPZ-105 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS Input Clock Rate Full 200 520 640 640 MHz Conversion Rate1 DCS Enabled Full 20 25 20 65 20 80 20 105 MSPS DCS Disabled Full 10 25 10 65 10 80 10 105 MSPS CLK Period—Divide-by-1 Full 40 15.4 12.5 9.5 ns Mode (tCLK) CLK Pulse Width High (tCH) Divide-by-1 Mode, DCS Full 12 20 28 4.65 7.70 10.75 3.75 6.25 8.75 2.85 4.75 6.65 ns Enabled Divide-by-1 Mode, DCS Full 19 20 21 7.33 7.70 8.07 5.95 6.25 6.55 4.5 4.75 5.0 ns Disabled Divide-by-2 Mode Full 0.8 0.8 0.8 0.8 ns Through Divide-by-8 Mode Aperture Delay (tA) Full 1.0 1.0 1.0 1.0 ns Aperture Uncertainty Full 0.100 0.090 0.080 0.075 ps rms (Jitter, tJ) DATA OUTPUT PARAMETERS CMOS Mode Data Propagation Delay Full 2.8 3.5 4.2 2.8 3.5 4.2 2.8 3.5 4.2 2.8 3.5 4.2 ns (tPD) DCO Propagation Delay Full 3.1 3.1 3.1 3.1 ns (tDCO)2 DCO to Data Skew (tSKEW) Full −0.6 −0.4 0 −0.6 −0.4 0 −0.6 −0.4 0 −0.6 −0.4 0 ns LVDS Mode Data Propagation Delay Full 2.9 3.7 4.5 2.9 3.7 4.5 2.9 3.7 4.5 2.9 3.7 4.5 ns (tPD) DCO Propagation Delay Full 3.9 3.9 3.9 3.9 ns (tDCO)2 DCO to Data Skew (tSKEW) Full −0.1 +0.2 +0.5 −0.1 +0.2 +0.5 −0.1 +0.2 +0.5 −0.1 +0.2 +0.5 ns CMOS Mode Pipeline Delay Full 12 12 12 12 Cycles (Latency) LVDS Mode Pipeline Delay Full 12/12.5 12/12.5 12/12.5 12/12.5 Cycles (Latency) Channel A/ Channel B Wake-Up Time3 Full 500 500 500 500 µs Out-of-Range Recovery Full 2 2 2 2 Cycles Time 1 Conversion rate is the clock rate after the divider. 2 Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17). 3 Wake-up time is defined as the time required to return to normal operation from power-down mode. Rev. B | Page 7 of 44 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9650-25 AD9650-65 AD9650-80 AD9650-105 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Common-Mode Voltage Servo Dither Large-Signal FFT Small-Signal FFT Static Linearity Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS SYNC Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next SYNC Only Bit 1—Clock Divider SYNC Enable Bit 0—Master SYNC Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE