Datasheet AD9649 (Analog Devices)

14-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter Data Sheet AD9649 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation AVDD GND SDIO SCLK CSB DRVDD 1.8 V to 3.3 V output supply SNR RBIAS SPI 74.3 dBFS at 9.7 MHz input VCM R OR PROGRAMMING DATA 71.5 dBFS at 200 MHz input FFE D13 (MSB) SFDR VIN+ S U ADC O CORE T B 93 dBc at 9.7 MHz input VIN– CM U D0 (LSB) TP 80 dBc at 200 MHz input OU DCO Low power VREF 45 mW at 20 MSPS SENSE 87 mW at 80 MSPS REF AD9649 SELECT Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit DIVIDE BY MODE 1, 2, 4 CONTROLS 2 V p-p differential analog input DNL = ±0.35 LSB
001
CLK+ CLK– PDWN DFS MODE Serial port control options
08539-
Offset binary, gray code, or twos complement data format
Figure 1.
Integer 1, 2, or 4 input clock divider Built-in selectable digital test pattern generation PRODUCT HIGHLIGHTS Energy-saving power-down modes
1. The AD9649 operates from a single 1.8 V analog power
Data clock out (DCO) with programmable clock and data
supply and features a separate digital output driver supply
alignment
to accommodate 1.8 V to 3.3 V logic families. 2. The sample-and-hold circuit maintains excel ent performance
APPLICATIONS
for input frequencies up to 200 MHz and is designed for low
Communications
cost, low power, and ease of use.
Diversity radio systems
3. A standard serial port interface (SPI) supports various
Multimode digital receivers
product features and functions, such as data output format-
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
ting, internal clock divider, power-down, DCO, data output
Smart antenna systems
(D13 to D0) timing and offset adjustments, and voltage
Battery-powered instruments
reference modes.
Handheld scope meters
4. The AD9649 is packaged in a 32-lead RoHS-compliant LFCSP
Portable medical imaging
that is pin compatible with the AD9629 12-bit ADC and
Ultrasound
the AD9609 10-bit ADC, enabling a simple migration path
Radar/LIDAR
between 10-bit and 14-bit converters sampling from 20 MSPS to 80 MSPS.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9649-80 AD9649-65 AD9649-40 AD9649-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS USR2 (Register 0x101) Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations Encode Clock VCM RBIAS Reference Decoupling SPI Port Soft Reset OUTLINE DIMENSIONS ORDERING GUIDE