Datasheet AD9649 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | 14-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter |
| Pages / Page | 33 / 3 — AD9649. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 2/2017—Rev. A to … |
| Revision | B |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
AD9649. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 2/2017—Rev. A to Rev. B. 6/2015—Rev. 0 to Rev. A
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AD9649 Data Sheet TABLE OF CONTENTS
Features .. 1 Voltage Reference ... 19 Applications ... 1 Clock Input Considerations .. 20 Functional Block Diagram .. 1 Power Dissipation and Standby Mode .. 21 Product Highlights ... 1 Digital Outputs ... 22 Revision History ... 2 Timing.. 22 General Description ... 3 Built-In Self-Test (BIST) and Output Test .. 23 Specifications ... 4 Built-In Self-Test (BIST) .. 23 DC Specifications ... 4 Output Test Modes ... 23 AC Specifications .. 5 Serial Port Interface (SPI) .. 24 Digital Specifications ... 6 Configuration Using the SPI ... 24 Switching Specifications .. 7 Hardware Interface ... 25 Timing Specifications .. 8 Configuration Without the SPI .. 25 Absolute Maximum Ratings .. 9 SPI Accessible Features .. 25 Thermal Characteristics .. 9 Memory Map .. 26 ESD Caution .. 9 Reading the Memory Map Register Table ... 26 Pin Configuration and Function Descriptions ... 10 Open Locations .. 26 Typical Performance Characteristics ... 11 Default Values ... 26 AD9649-80 .. 11 Memory Map Register Table ... 27 AD9649-65 .. 13 Memory Map Register Descriptions .. 29 AD9649-40 .. 14 Applications Information .. 30 AD9649-20 .. 15 Design Guidelines .. 30 Equivalent Circuits ... 16 Outline Dimensions ... 31 Theory of Operation .. 17 Ordering Guide .. 31 Analog Input Considerations .. 17
REVISION HISTORY 2/2017—Rev. A to Rev. B
Added Endnote 1, Table 16 ... 28 Changes to Power and Ground Recommendations Section ... 30 Added Soft Reset Section ... 30
6/2015—Rev. 0 to Rev. A
Change to Product Highlights Section .. 1 Changes to Figure 3 and Table 8 ... 10 Updated Outline Dimensions ... 32 Changes to Ordering Guide .. 32
10/2009—Revision 0: Initial Version
Rev. B | Page 2 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9649-80 AD9649-65 AD9649-40 AD9649-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS USR2 (Register 0x101) Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations Encode Clock VCM RBIAS Reference Decoupling SPI Port Soft Reset OUTLINE DIMENSIONS ORDERING GUIDE
AD9649 Data Sheet TABLE OF CONTENTS
Features .. 1 Voltage Reference ... 19 Applications ... 1 Clock Input Considerations .. 20 Functional Block Diagram .. 1 Power Dissipation and Standby Mode .. 21 Product Highlights ... 1 Digital Outputs ... 22 Revision History ... 2 Timing.. 22 General Description ... 3 Built-In Self-Test (BIST) and Output Test .. 23 Specifications ... 4 Built-In Self-Test (BIST) .. 23 DC Specifications ... 4 Output Test Modes ... 23 AC Specifications .. 5 Serial Port Interface (SPI) .. 24 Digital Specifications ... 6 Configuration Using the SPI ... 24 Switching Specifications .. 7 Hardware Interface ... 25 Timing Specifications .. 8 Configuration Without the SPI .. 25 Absolute Maximum Ratings .. 9 SPI Accessible Features .. 25 Thermal Characteristics .. 9 Memory Map .. 26 ESD Caution .. 9 Reading the Memory Map Register Table ... 26 Pin Configuration and Function Descriptions ... 10 Open Locations .. 26 Typical Performance Characteristics ... 11 Default Values ... 26 AD9649-80 .. 11 Memory Map Register Table ... 27 AD9649-65 .. 13 Memory Map Register Descriptions .. 29 AD9649-40 .. 14 Applications Information .. 30 AD9649-20 .. 15 Design Guidelines .. 30 Equivalent Circuits ... 16 Outline Dimensions ... 31 Theory of Operation .. 17 Ordering Guide .. 31 Analog Input Considerations .. 17
REVISION HISTORY 2/2017—Rev. A to Rev. B
Added Endnote 1, Table 16 ... 28 Changes to Power and Ground Recommendations Section ... 30 Added Soft Reset Section ... 30
6/2015—Rev. 0 to Rev. A
Change to Product Highlights Section .. 1 Changes to Figure 3 and Table 8 ... 10 Updated Outline Dimensions ... 32 Changes to Ordering Guide .. 32
10/2009—Revision 0: Initial Version
Rev. B | Page 2 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9649-80 AD9649-65 AD9649-40 AD9649-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS USR2 (Register 0x101) Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations Encode Clock VCM RBIAS Reference Decoupling SPI Port Soft Reset OUTLINE DIMENSIONS ORDERING GUIDE
