Datasheet AD9230-11 (Analog Devices) - 10

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AD9230-11 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ) ) B B S S D D L L ( ( + – N D D – + D + – + – C C O O G V D K K D 1 1 0 0 N N C C R R V L L V D D D D D D D D D D A C C A 6 5 4 3 2 1 0 9 8 7 6 5 5 5 5 5 5 4 3 5 5 4 4 4 4 4 4 4 D2– 1 PIN 1 42 AVDD INDICATOR D2+ 2 41 AVDD D3– 3 40 CML D3+ 4 39 AVDD D4– 5 38 AVDD D4+ 6 37 AVDD AD9230-11 DRVDD 7 36 VIN– DRGND 8 TOP VIEW 35 VIN+ D5– 9 (Not to Scale) 34 AVDD D5+ 10 33 AVDD D6– 11 32 AVDD D6+ 12 31 RBIAS D7– 13 30 AVDD D7+ 14 29 PWDN 5 6 7 8 0 1 1 1 1 91 2 2 22 32 42 52 62 72 8 1 2 – + + – 8 + – + T 8 9 – 9 0 0 S S B R D D E D R F D D D 1 1 N D C S D O O D D C S D G V / / ) ) R R K E B O B D D I L R S S D C M S ( M S ( NOTES
4
1. DNC = DO NOT CONNECT.
-00 01
2. PIN 0 (EXPOSED PADDLE) = AGND.
71 0 Figure 4. Single Data Rate Mode Pin Configuration
Table 7. Single Data Rate Mode Pin Function Descriptions Pin No. Mnemonic Description
30, 32 to 34, 37 to 39, 41 to AVDD 1.8 V Analog Supply. 43, 46 7, 24, 47 DRVDD 1.8 V Digital Output Supply. 0 AGND1 Analog Ground. The exposed paddle should be connected to the analog ground. 8, 23, 48 DRGND1 Digital Output Ground. 35 VIN+ Analog Input (True). 36 VIN− Analog Input (Complement). 40 CML Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+/VIN−. 44 CLK+ Clock Input (True). 45 CLK− Clock Input (Complement). 31 RBIAS Set Pin for Chip Bias Current. Place 1% 10 kΩ resistor terminated to ground. Nominally 0.5 V. 28 RESET CMOS-Compatible Chip Reset (Active Low). 25 SDIO/DCS Serial Port Interface (SPI) Data Input/Output (Serial Port Mode). Duty Cycle Stabilizer Select (External Pin Mode). 26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode). Data Format Select Pin (External Pin Mode). 27 CSB Serial Port Chip Select (Active Low). 29 PWDN Chip Power-Down. 49 DCO− Data Clock Output (Complement). 50 DCO+ Data Clock Output Input (True). 51, 52 DNC Do No Connect. 53 D0− (LSB) D0 Complement Output Bit (LSB). 54 D0+ (LSB) D0 True Output Bit (LSB). 55 D1− D1 Complement Output Bit. 56 D1+ D1 True Output Bit. 1 D2− D2 Complement Output Bit. 2 D2+ D2 True Output Bit. Rev. 0 | Page 9 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS TRANSFER REGISTER MAP OUTLINE DIMENSIONS ORDERING GUIDE