Datasheet AD7765 (Analog Devices) - 9

ManufacturerAnalog Devices
Description24-Bit, 156 kSPS, 112 dB Sigma-Delta ADC with On-Chip Buffers and Serial Interface
Pages / Page33 / 9 — AD7765. ABSOLUTE MAXIMUM RATINGS. Table 4. Parameters. Rating. ESD CAUTION
RevisionC
File Format / SizePDF / 896 Kb
Document LanguageEnglish

AD7765. ABSOLUTE MAXIMUM RATINGS. Table 4. Parameters. Rating. ESD CAUTION

AD7765 ABSOLUTE MAXIMUM RATINGS Table 4 Parameters Rating ESD CAUTION

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AD7765 ABSOLUTE MAXIMUM RATINGS
T Stresses above those listed under Absolute Maximum Ratings A = 25°C, unless otherwise noted. may cause permanent damage to the device. This is a stress
Table 4.
rating only; functional operation of the device at these or any
Parameters Rating
other conditions above those listed in the operational sections AVDD1 to GND −0.3 V to +2.8 V of this specification is not implied. Exposure to absolute AVDD2, AVDD3, AVDD4 to GND −0.3 V to +6 V maximum rating conditions for extended periods may affect DVDD to GND −0.3 V to +2.8 V device reliability. VINA+, VINA− to GND1 −0.3 V to +6 V VIN+, VIN− to GND1 −0.3 V to +6 V
ESD CAUTION
Digital Input Voltage to GND2 −0.3 V to +2.8 V VREF+ to GND3 −0.3 V to +6 V Input Current to Any Pin Except Supplies4 ±10 mA Operating Temperature Range Commercial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package θJA Thermal Impedance 143°C/W θJC Thermal Impedance 45°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD 1 kV 1 Absolute maximum voltage for VIN−, VIN+, VINA−, and VINA+ is 6.0 V or AVDD3 + 0.3 V, whichever is lower. 2 Absolute maximum voltage on digital inputs is 3.0 V or DVDD + 0.3 V, whichever is lower. 3 Absolute maximum voltage on VREF+ input is 6.0 V or AVDD4 + 0.3 V, whichever is lower. 4 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. A | Page 8 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Σ-Δ Modulation and Digital Filtering AD7765 Antialias Protection AD7765 Input Structure On-Chip Differential Amplifier Modulator Input Structure Driving the Modulator Inputs Directly AD7765 Interface Reading Data Reading Status and Other Registers Writing to the AD7765 AD7765 Functionality Synchronization Overrange Alerts Power Modes Low Power Mode RESET/PWRDWN Mode Decimation Rate Pin Daisy Chaining Reading Data in Daisy-Chain Mode Writing Data in Daisy-Chain Mode Clocking the AD7765 MCLK Jitter Requirements Example 1 Example 2 Decoupling and Layout Information Supply Decoupling Reference Voltage Filtering Differential Amplifier Components Layout Considerations Using the AD7765 Bias Resistor Selection AD7765 Registers Control Register Status Register Gain Register—Address 0x0004 Non-Bit-Mapped, Default Value 0xA000 Overrange Register—Address 0x0005 Non-Bit-Mapped, Default Value 0xCCCC Outline Dimensions Ordering Guide