Datasheet AD7765 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 24-Bit, 156 kSPS, 112 dB Sigma-Delta ADC with On-Chip Buffers and Serial Interface |
| Pages / Page | 33 / 10 — AD7765. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. INA–. AVDD3. OUTA+. … |
| Revision | C |
| File Format / Size | PDF / 896 Kb |
| Document Language | English |
AD7765. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. INA–. AVDD3. OUTA+. VREF+. INA+. REFGND. OUTA–. AVDD4. IN–. AVDD1. IN+. AGND1. TOP VIEW. DD2
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AD7765 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V 1 28 INA– AVDD3 V 2 27 OUTA+ VREF+ V 3 26 INA+ REFGND V 4 25 OUTA– AVDD4 V 5 24 IN– AVDD1 V 6 AD7765 23 IN+ AGND1 AV 7 TOP VIEW 22 DD2 RBIAS (Not to Scale) AGND3 8 21 AVDD2 OVERRANGE 9 20 AGND2 SCO 10 19 MCLK FSO 11 18 DEC_RATE SDO 12 17 DVDD SDI 13 16 RESET/PWRDWN
005
FSI 14 15 SYNC
06519- Figure 5. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
24 AVDD1 2.5 V Power Supply for Modulator. This pin should be decoupled to AGND1 (Pin 23) with a 100 nF capacitor. 7 and 21 AVDD2 5 V Power Supply. Pin 7 should be decoupled to AGND3 (Pin 8) with a 100 nF capacitor. Pin 21 should be decoupled to AGND1 (Pin 23) with a 100 nF capacitor. 28 AVDD3 3.3 V to 5 V Power Supply for Differential Amplifier. This pin should be decoupled to the ground plane with a 100 nF capacitor. 25 AVDD4 3.3 V to 5 V Power Supply for Reference Buffer. This pin should be decoupled to AGND1 (Pin 23) with a 100 nF capacitor. 17 DVDD 2.5 V Power Supply for Digital Circuitry and FIR Filter. This pin should be decoupled to the ground plane with a 100 nF capacitor. 22 RBIAS Bias Current Setting Pin. This pin must be decoupled to the ground plane. For more details, see the Bias Resistor Selection section. 23 AGND1 Power Supply Ground for Analog Circuitry. 20 AGND2 Power Supply Ground for Analog Circuitry. 8 AGND3 Power Supply Ground for Analog Circuitry. 26 REFGND Reference Ground. Ground connection for the reference voltage. 27 VREF+ Reference Input. 1 VINA− Negative Input to Differential Amplifier. 2 VOUTA+ Positive Output from Differential Amplifier. 3 VINA+ Positive Input to Differential Amplifier. 4 VOUTA− Negative Output from Differential Amplifier. 5 VIN− Negative Input to the Modulator. 6 VIN+ Positive Input to the Modulator. 9 OVERRANGE Overrange Pin. This pin outputs a logic high to indicate that the user has applied an analog input that is approaching the limit of the analog input to the modulator. 10 SCO Serial Clock Out. This clock signal is derived from the internal ICLK signal. The frequency of this clock is equal to ICLK. See the Clocking the AD7765 section for further details. 11 FSO Frame Sync Out. This signal frames the serial data output and is 32 SCO periods wide. 12 SDO Serial Data Out. Data and status are output on this pin during each serial transfer. Each bit is clocked out on an SCO rising edge and is valid on the falling edge. See the AD7765 Interface section for further details. 13 SDI Serial Data In. The first data bit (MSB) must be valid on the next SCO falling edge after the FSI event is latched. Thirty-two bits are required for each write; the first 16-bit word contains the device and register address and the second word contains the data. See the AD7765 Interface section for further details. Rev. A | Page 9 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Σ-Δ Modulation and Digital Filtering AD7765 Antialias Protection AD7765 Input Structure On-Chip Differential Amplifier Modulator Input Structure Driving the Modulator Inputs Directly AD7765 Interface Reading Data Reading Status and Other Registers Writing to the AD7765 AD7765 Functionality Synchronization Overrange Alerts Power Modes Low Power Mode RESET/PWRDWN Mode Decimation Rate Pin Daisy Chaining Reading Data in Daisy-Chain Mode Writing Data in Daisy-Chain Mode Clocking the AD7765 MCLK Jitter Requirements Example 1 Example 2 Decoupling and Layout Information Supply Decoupling Reference Voltage Filtering Differential Amplifier Components Layout Considerations Using the AD7765 Bias Resistor Selection AD7765 Registers Control Register Status Register Gain Register—Address 0x0004 Non-Bit-Mapped, Default Value 0xA000 Overrange Register—Address 0x0005 Non-Bit-Mapped, Default Value 0xCCCC Outline Dimensions Ordering Guide
AD7765 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V 1 28 INA– AVDD3 V 2 27 OUTA+ VREF+ V 3 26 INA+ REFGND V 4 25 OUTA– AVDD4 V 5 24 IN– AVDD1 V 6 AD7765 23 IN+ AGND1 AV 7 TOP VIEW 22 DD2 RBIAS (Not to Scale) AGND3 8 21 AVDD2 OVERRANGE 9 20 AGND2 SCO 10 19 MCLK FSO 11 18 DEC_RATE SDO 12 17 DVDD SDI 13 16 RESET/PWRDWN
005
FSI 14 15 SYNC
06519- Figure 5. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
24 AVDD1 2.5 V Power Supply for Modulator. This pin should be decoupled to AGND1 (Pin 23) with a 100 nF capacitor. 7 and 21 AVDD2 5 V Power Supply. Pin 7 should be decoupled to AGND3 (Pin 8) with a 100 nF capacitor. Pin 21 should be decoupled to AGND1 (Pin 23) with a 100 nF capacitor. 28 AVDD3 3.3 V to 5 V Power Supply for Differential Amplifier. This pin should be decoupled to the ground plane with a 100 nF capacitor. 25 AVDD4 3.3 V to 5 V Power Supply for Reference Buffer. This pin should be decoupled to AGND1 (Pin 23) with a 100 nF capacitor. 17 DVDD 2.5 V Power Supply for Digital Circuitry and FIR Filter. This pin should be decoupled to the ground plane with a 100 nF capacitor. 22 RBIAS Bias Current Setting Pin. This pin must be decoupled to the ground plane. For more details, see the Bias Resistor Selection section. 23 AGND1 Power Supply Ground for Analog Circuitry. 20 AGND2 Power Supply Ground for Analog Circuitry. 8 AGND3 Power Supply Ground for Analog Circuitry. 26 REFGND Reference Ground. Ground connection for the reference voltage. 27 VREF+ Reference Input. 1 VINA− Negative Input to Differential Amplifier. 2 VOUTA+ Positive Output from Differential Amplifier. 3 VINA+ Positive Input to Differential Amplifier. 4 VOUTA− Negative Output from Differential Amplifier. 5 VIN− Negative Input to the Modulator. 6 VIN+ Positive Input to the Modulator. 9 OVERRANGE Overrange Pin. This pin outputs a logic high to indicate that the user has applied an analog input that is approaching the limit of the analog input to the modulator. 10 SCO Serial Clock Out. This clock signal is derived from the internal ICLK signal. The frequency of this clock is equal to ICLK. See the Clocking the AD7765 section for further details. 11 FSO Frame Sync Out. This signal frames the serial data output and is 32 SCO periods wide. 12 SDO Serial Data Out. Data and status are output on this pin during each serial transfer. Each bit is clocked out on an SCO rising edge and is valid on the falling edge. See the AD7765 Interface section for further details. 13 SDI Serial Data In. The first data bit (MSB) must be valid on the next SCO falling edge after the FSI event is latched. Thirty-two bits are required for each write; the first 16-bit word contains the device and register address and the second word contains the data. See the AD7765 Interface section for further details. Rev. A | Page 9 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Σ-Δ Modulation and Digital Filtering AD7765 Antialias Protection AD7765 Input Structure On-Chip Differential Amplifier Modulator Input Structure Driving the Modulator Inputs Directly AD7765 Interface Reading Data Reading Status and Other Registers Writing to the AD7765 AD7765 Functionality Synchronization Overrange Alerts Power Modes Low Power Mode RESET/PWRDWN Mode Decimation Rate Pin Daisy Chaining Reading Data in Daisy-Chain Mode Writing Data in Daisy-Chain Mode Clocking the AD7765 MCLK Jitter Requirements Example 1 Example 2 Decoupling and Layout Information Supply Decoupling Reference Voltage Filtering Differential Amplifier Components Layout Considerations Using the AD7765 Bias Resistor Selection AD7765 Registers Control Register Status Register Gain Register—Address 0x0004 Non-Bit-Mapped, Default Value 0xA000 Overrange Register—Address 0x0005 Non-Bit-Mapped, Default Value 0xCCCC Outline Dimensions Ordering Guide
