Datasheet AD9246 (Analog Devices)

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter AD9246 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation AVDD DRVDD 1.8 V to 3.3 V output supply AD9246 SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input VIN+ 8-STAGE SFDR = 85 dBc to 70 MHz input SHA MDAC1 A/D VIN– 1 1/2-BIT PIPELINE Low power: 395 mW @ 125 MSPS 4 8 3 Differential input with 650 MHz bandwidth REFT A/D On-chip voltage reference and sample-and-hold amplifier REFB CORRECTION LOGIC OR DNL = ±0.4 LSB 15 Flexible analog input: 1 V p-p to 2 V p-p range OUTPUT BUFFERS DCO Offset binary, Gray code, or twos complement data format D13 (MSB) Clock duty cycle stabilizer VREF D0 (LSB) Data output clock SENSE SCLK/DFS 0.5V CLOCK Serial port control DUTY CYCLE MODE SELECT SDIO/DCS REF STABILIZER Built-in selectable digital test pattern generation CSB SELECT Programmable clock and data alignment
01 0
AGND CLK+ CLK– PDWN DRGND
05491-
APPLICATIONS
Figure 1.
Ultrasound equipment IF sampling in communications receivers IS-95, CDMA-One, IMT-2000 Battery-powered instruments Hand-held scopemeters
The digital output data is presented in offset binary, Gray code, or
Low cost digital oscilloscopes
twos complement formats. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic.
GENERAL DESCRIPTION
The AD9246 is a monolithic, single 1.8 V supply, 14-bit, 80 MSPS/ The AD9246 is available in a 48-lead LFCSP_VQ and is specified 105 MSPS/125 MSPS analog-to-digital converter (ADC), featuring over the industrial temperature range (−40°C to +85°C). a high performance sample-and-hold amplifier (SHA) and on-chip
PRODUCT HIGHLIGHTS
voltage reference. The product uses a multistage differential pipeline architecture with output error correction logic to 1. The AD9246 operates from a single 1.8 V power supply provide 14-bit accuracy at 125 MSPS data rates and guarantees and features a separate digital output driver supply to no missing codes over the full operating temperature range. accommodate 1.8 V to 3.3 V logic families. The wide bandwidth, truly differential SHA allows a variety of 2. The patented SHA input maintains excellent performance user-selectable input ranges and offsets, including single-ended for input frequencies up to 225 MHz. applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling 3. The clock DCS maintains overall ADC performance over a single-channel inputs at frequencies well beyond the Nyquist rate. wide range of clock pulse widths. Combined with power and cost savings over previously available ADCs, the AD9246 is suitable for applications in communications, 4. A standard serial port interface supports various product imaging, and medical ultrasound. features and functions, such as data formatting (offset binary, twos complement, or Gray coding), enabling the A differential clock input controls all internal conversion cycles. clock DCS, power-down, and voltage reference mode. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC 5. The AD9246 is pin-compatible with the AD9233, allowing performance. a simple migration from 12 bits to 14 bits.
Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS JITTER CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS TIMING SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER TABLE LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS CML RBIAS REFERENCE DECOUPLING EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS ALTERNATIVE CLOCK CONFIGURATIONS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION SCHEMATICS EVALUATION BOARD LAYOUTS BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE