Datasheet AD9215 (Analog Devices) - 8

Data Sheet AD9215 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS D D D D T B D N – + N D F F V G NI NI G V E E A A V V A A R R 2 1 0 9 8 7 6 5 OR 1 28 D9 (MSB) 3 3 3 2 2 2 2 2 MODE 2 27 D8 DNC 1 24 VREF SENSE 3 26 D7 CLK 2 23 SENSE DNC 3 22 MODE VREF 4 25 D6 AD9215 PDWN 4 21 OR REFB 5 24 DRVDD DNC 5 TOP VIEW 20 D9 (MSB) (Not to Scale) DNC 6 19 D8 REFT 6 23 DRGND AD9215 DNC 7 18 D7 AVDD 7 TOP VIEW 22 D5 (Not to Scale) DNC 8 17 D6 AGND 8 21 D4 9 0 1 2 3 4 5 6 VIN+ 9 20 D3 1 1 1 1 1 1 1 0 1 2 3 4 5 D D D D D D D D VIN– 10 N D 19 D2 ) B G V S R R AGND 11 18 D1 L D D ( AVDD 12 17 D0 (LSB) NOTES 1. DNC = DO NOT CONNECT. CLK 13 16 DNC 2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE. THERE IS PDWN 14 15 DNC
4
AN INCREASED RELIABILITY OF THE SOLDER JOINTS, AND
-003 0 -0
THE MAXIMUM THERMAL CAPABILITY OF THE PACKAGE IS
-A 4
DNC = DO NOT CONNECT ACHIEVED WITH THE EXPOSED PAD SOLDERED TO THE
7 02874-A 8
CUSTOMER BOARD.
2 0 Figure 3. TSSOP (RU-28) Figure 4. LFCSP (CP-32-7)
Table 6. Pin Function Descriptions TSSOP Pin No. LFCSP Pin No. Mnemonic Description
1 21 OR Out-of-Range Indicator. 2 22 MODE Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection. 3 23 SENSE Reference Mode Selection. 4 24 VREF Voltage Reference Input/Output. 5 25 REFB Differential Reference (Negative). 6 26 REFT Differential Reference (Positive). 7, 12 27, 32 AVDD Analog Power Supply. 8, 11 28, 31 AGND Analog Ground. 9 29 VIN+ Analog Input Pin (+). 10 30 VIN− Analog Input Pin (−). 13 2 CLK Clock Input Pin. 14 4 PDWN Power-Down Function Selection (Active High). 15 to 16 1, 3, 5 to 8 DNC Do not connect, recommend floating this pin. 17 to 22, 9 to 14, D0 (LSB) to Data Output Bits. 25 to 28 17 to 20 D9 (MSB) 23 15 DRGND Digital Output Ground. 24 16 DRVDD Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 μF capacitor. Recommended decoupling is 0.1 μF in parallel with 10 μF. N/A 33 EP Exposed Pad. It is recommended that the exposed pad be soldered to the ground plane for the LFCSP package. There is an increased reliability of the solder joints, and the maximum thermal capability of the package is achieved with the exposed pad soldered to the customer board. Rev. B | Page 7 of 36 Document Outline Specifications Absolute Maximum Ratings1 Explanation of Test Levels ESD Caution Pin Configurations and Function Descriptions Equivalent Circuits Definitions of Specifications Aperture Delay Aperture Jitter Clock Pulse Width and Duty Cycle Differential Nonlinearity (DNL, No Missing Codes) Effective Number of Bits (ENOB) Gain Error Integral Nonlinearity (INL) Maximum Conversion Rate Minimum Conversion Rate Offset Error Out-of-Range Recovery Time Output Propagation Delay Power Supply Rejection Signal-to-Noise and Distortion (SINAD) Ratio Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Temperature Drift Total Harmonic Distortion (THD) Two-Tone SFDR Typical Performance Characteristics Applying the AD9215 Theory of Operation Analog Input and Reference Overview Differential Input Configurations Single-Ended Input Configuration Clock Input and Considerations Power Dissipation and Standby Mode Digital Outputs Timing Voltage Reference Internal Reference Connection External Reference Operation Operational Mode Selection Evaluation Board Outline Dimensions Ordering Guide