Datasheet AD9215 (Analog Devices) - 9

AD9215 Data Sheet EQUIVALENT CIRCUITS AVDD
no missing codes to 10-bit resolution indicate that al 1024 codes, respectively, must be present over al operating ranges.
Effective Number of Bits (ENOB) MODE
For a sine wave, SINAD can be expressed in terms of the num- ber of bits. Using the following formula, it is possible to obtain a measure of performance expressed as N, the effective number of 02874-A-005 Figure 5. Equivalent Analog Input Circuit bits
AVDD
N = (SINAD – 1.76)/6.02 Thus, the effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly
MODE
from its measured SINAD.
20k
Ω
Gain Error
02874-A-006 Figure 6. Equivalent MODE Input Circuit The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at
DRVDD
an analog value 1 1/2 LSB below the positive full scale. Gain error is the deviation of the actual difference between the first
D9–D0,
and last code transitions and the ideal difference between the
OR
first and last code transitions.
Integral Nonlinearity (INL)
02874-A-007 Figure 7. Equivalent Digital Output Circuit INL refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.”
AVDD
The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2
2.6k
Ω LSB beyond the last code transition. The deviation is measured
CLK
from the middle of each particular code to the true straight line.
2.6k
Ω
Maximum Conversion Rate
02874-A-008 Figure 8. Equivalent Digital Input Circuit The clock rate at which parametric testing is performed.
Minimum Conversion Rate DEFINITIONS OF SPECIFICATIONS
The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed
Aperture Delay
limit. Aperture delay is a measure of the sample-and-hold amplifier
Offset Error
(SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. The major carry transition should occur for an analog value 1/2 LSB below VIN+ = VIN−. Zero error is defined as the deviation
Aperture Jitter
of the actual transition from that point. Aperture jitter is the variation in aperture delay for successive
Out-of-Range Recovery Time
samples and can be manifested as frequency-dependent noise on the input to the ADC. Out-of-range recovery time is the time it takes for the ADC to reacquire the analog input after a transient from 10% above
Clock Pulse Width and Duty Cycle
positive full scale to 10% above negative full scale, or from 10% Pulse width high is the minimum amount of time that the clock below negative full scale to 10% below positive full scale. pulse should be left in the Logic 1 state to achieve rated perfor- mance. Pulse width low is the minimum time the clock pulse
Output Propagation Delay
should be left in the low state. At a given clock rate, these speci- The delay between the clock logic threshold and the time when fications define an acceptable clock duty cycle. all bits are within valid logic levels.
Differential Nonlinearity (DNL, No Missing Codes) Power Supply Rejection
An ideal ADC exhibits code transitions that are exactly 1 LSB The specification shows the maximum change in ful scale from apart. DNL is the deviation from this ideal value. Guaranteed the value with the supply at the minimum limit to the value Rev. B | Page 8 of 36 Document Outline Specifications Absolute Maximum Ratings1 Explanation of Test Levels ESD Caution Pin Configurations and Function Descriptions Equivalent Circuits Definitions of Specifications Aperture Delay Aperture Jitter Clock Pulse Width and Duty Cycle Differential Nonlinearity (DNL, No Missing Codes) Effective Number of Bits (ENOB) Gain Error Integral Nonlinearity (INL) Maximum Conversion Rate Minimum Conversion Rate Offset Error Out-of-Range Recovery Time Output Propagation Delay Power Supply Rejection Signal-to-Noise and Distortion (SINAD) Ratio Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Temperature Drift Total Harmonic Distortion (THD) Two-Tone SFDR Typical Performance Characteristics Applying the AD9215 Theory of Operation Analog Input and Reference Overview Differential Input Configurations Single-Ended Input Configuration Clock Input and Considerations Power Dissipation and Standby Mode Digital Outputs Timing Voltage Reference Internal Reference Connection External Reference Operation Operational Mode Selection Evaluation Board Outline Dimensions Ordering Guide