Datasheet AD9430 (Analog Devices)

12-Bit, 170/210 MSPS 3.3 V A/D Converter AD9430 FEATURES FUNCTIONAL BLOCK DIAGRAM SNR = 65 dB @ fIN = 70 MHz @ 210 MSPS SENSE VREF AGND DRGND DRVDD AVDD ENOB of 10.6 @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS) AD9430 SFDR = 80 dBc @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS) SCALABLE Excellent linearity: REFERENCE DNL = ±0.3 LSB (typical) INL = ±0.5 LSB (typical) LVDS OUTPUTS 2 output data options: VIN+ ADC DATA, 12 TRACK- 12-BIT OVERRANGE Demultiplexed 3.3 V CMOS outputs each @ 105 MSPS AND-HOLD PIPELINE IN LVDS OR VIN– CORE 2-PORT CMOS CMOS Interleaved or parallel data output option OUTPUTS LVDS at 210 MSPS DS+ 700 MHz full-power analog bandwidth DS– CLOCK SELECT CMOS DCO+ On-chip reference and track-and-hold MANAGEMENT OR LVDS CLK+ DCO– Power dissipation = 1.3 W typical @ 210 MSPS CLK– 1.5 V input voltage range
02607-001
3.3 V supply operation S1 S2 S4 S5 Output data format option
Figure 1.
Data sync input and data clock output provided Clock duty cycle stabilizer GENERAL DESCRIPTION APPLICATIONS
The AD9430 is a 12-bit, monolithic, sampling analog-to-digital
Wireless and wired broadband communications
converter (ADC) optimized for high performance, low power,
Cable reverse path
and ease of use. The product operates up to a 210 MSPS
Communications test equipment
conversion rate and is optimized for outstanding dynamic
Radar and satellite subsystems
performance in wideband carrier and broadband systems. All
Power amplifier linearization
necessary functions, including a track-and-hold (T/H) and reference, are included on the chip to provide a complete
PRODUCT HIGHLIGHTS
conversion solution. 1. High performance. The ADC requires a 3.3 V power supply and a differential Maintains 65 dB SNR @ 210 MSPS with a 65 MHz input. ENCODE clock for full performance operation. The digital 2. Low power. outputs are TTL/CMOS or LVDS compatible and support either Consumes only 1.3 W @ 210 MSPS. twos complement or offset binary format. Separate output 3. Ease of use. power supply pins support interfacing with 3.3 V CMOS logic. LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and Two output buses support demultiplexed data up to 105 MSPS sample-and-hold provide flexibility in system design. Use rates in CMOS mode. A data sync input is supported for proper of a single 3.3 V supply simplifies system power supply output data port alignment in CMOS mode, and a data clock design. output is available for proper output data timing. In LVDS 4. Out of range (OR) feature. mode, the chip provides data at the ENCODE clock rate. The OR output bit indicates when the input signal is Fabricated on an advanced BiCMOS process, the AD9430 is beyond the selected input range. available in a 100-lead, surface-mount plastic package 5. Pin compatible with 10-bit AD9411 (LVDS only). (100 e-PAD TQFP) specified over the industrial temperature . range (–40°C to +85°C).
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Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION APPLICATIONS TABLE OF CONTENTS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY APPLICATION NOTES THEORY OF OPERATION ENCODE INPUT ANALOG INPUT DS INPUTS (DS+, DS–) CMOS OUTPUTS LVDS OUTPUTS VOLTAGE REFERENCE NOISE POWER RATIO TESTING (NPR) EVALUATION BOARD, CMOS MODE POWER CONNECTOR ANALOG INPUTS GAIN ENCODE VOLTAGE REFERENCE DATA FORMAT SELECT I/P TIMING SELECT TIMING CONTROLS CMOS DATA OUTPUTS CRYSTAL OSCILLATOR OPTIONAL AMPLIFIER TROUBLESHOOTING EVALUATION BOARD, LVDS MODE POWER CONNECTOR ANALOG INPUTS GAIN CLOCK VOLTAGE REFERENCE DATA FORMAT SELECT DATA OUTPUTS CRYSTAL OSCILLATOR OUTLINE DIMENSIONS ORDERING GUIDE