Datasheet AD7490 (Analog Devices) - 11

ManufacturerAnalog Devices
Description16-Channel, 1MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP
Pages / Page29 / 11 — AD7490. Data Sheet. TERMINOLOGY Integral Nonlinearity. Negative Gain …
RevisionD
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AD7490. Data Sheet. TERMINOLOGY Integral Nonlinearity. Negative Gain Error Match. Channel-to-Channel Isolation

AD7490 Data Sheet TERMINOLOGY Integral Nonlinearity Negative Gain Error Match Channel-to-Channel Isolation

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AD7490 Data Sheet TERMINOLOGY Integral Nonlinearity Negative Gain Error Match
This is the maximum deviation from a straight line passing This is the difference in negative gain error between any two through the endpoints of the ADC transfer function. The end- channels. points of the transfer function are zero scale, a point 1 LSB
Channel-to-Channel Isolation
below the first code transition, and full scale, a point 1 LSB Channel-to-channel isolation is a measure of the level of above the last code transition. crosstalk between channels. It is measured by applying a full-
Differential Nonlinearity
scale 400 kHz sine wave signal to all 15 nonselected input This is the difference between the measured and the ideal 1 LSB channels and determining how much that signal is attenuated in change between any two adjacent codes in the ADC. the selected channel with a 50 kHz signal. This specification is
Offset Error
the worst case across all 16 channels for the AD7490. This is the deviation of the first code transition (00 … 000) to
PSR (Power Supply Rejection)
(00 … 001) from the ideal, that is, AGND + 1 LSB. Variations in power supply affect the full scale transition, but
Offset Error Match
not the converter linearity. Power supply rejection is the This is the difference in offset error between any two channels. maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value. (see
Gain Error
the Typical Performance Characteristics section). This is the deviation of the last code transition (111 … 110) to (111 … 111) from the ideal (that is, REF
Track-and-Hold Acquisition Time
IN − 1 LSB) after the offset error has been adjusted out. The track-and-hold amplifier returns into track on the 14th SCLK falling edge. Track-and-hold acquisition time is the
Gain Error Match
minimum time required for the track-and-hold amplifier to This is the difference in gain error between any two channels. remain in track mode for its output to reach and settle to within
Zero Code Error
±1 LSB of the applied input signal, given a step change to the This applies when using the twos complement output coding input signal. option, in particular to the 2 × REFIN input range with −REFIN
Signal-to-(Noise + Distortion) Ratio
to +REFIN biased about the REFIN point. It is the deviation of the This is the measured ratio of signal to (noise + distortion) at the midscale transition (all 0s to all 1s) from the ideal VIN voltage, output of the analog-to-digital converter. The signal is the rms that is, REFIN − 1 LSB. amplitude of the fundamental. Noise is the sum of al nonfunda-
Zero Code Error Match
mental signals up to half the sampling frequency (fS/2), excluding This is the difference in zero code error between any two dc. The ratio is dependent on the number of quantization levels channels. in the digitization process; the more levels, the smaller the quan-
Positive Gain Error
tization noise. The theoretical signal-to-(noise + distortion) ratio This applies when using the twos complement output coding for an ideal N-bit converter with a sine wave input is given by option, in particular the 2 × REFIN input range with −REFIN to Signal-to-(Noise + Distortion) (dB) = 6.02N + 1.76 +REFIN biased about the REFIN point. It is the deviation of the Thus for a 12-bit converter, this is 74 dB. last code transition (011 … 110) to (011 … 111) from the ideal (that is, +REF
Total Harmonic Distortion
IN − 1 LSB) after the zero code error has been adjusted out. Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7490, it is defined as
Positive Gain Error Match
This is the difference in positive gain error between any two 2 2 2 2 2 + + + + THD(dB) 2 V 3 V 4 V 5 V 6 V = × channels. 20 log 1 V
Negative Gain Error
where V1 is the rms amplitude of the fundamental and V2, V3, This applies when using the twos complement output coding V4, V5, and V6 are the rms amplitudes of the second through the option, in particular to the 2 × REFIN input range with −REFIN sixth harmonics. to +REFIN biased about the REFIN point. It is the deviation of the first code transition (100 … 000) to (100 … 001) from the ideal (that is, −REFIN + 1 LSB) after the zero code error has been adjusted out. Rev. D | Page 10 of 28 Document Outline Features Functional Block Diagram General Description Product Highlights Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Internal Register Structure Control Register Sequencer Operation Shadow Register Theory of Operation Circuit Information Converter Operation Analog Input ADC Transfer Function Handling Bipolar Input Signals Typical Connection Diagram Analog Input Channels Digital Input VDRIVE Reference Section Modes of Operation Normal Mode (PM1 = PM0 = 1) Full Shutdown (PM1 = 1, PM0 = 0) Auto Shutdown (PM1 = 0, PM0 = 1) Auto Standby (PM1 = PM0 = 0) Powering Up the AD7490 Serial Interface Power vs. Throughput Rate Microprocessor Interfacing AD7490 to TMS320C541 AD7490 to ADSP-21xx AD7490 to DSP563xx Application Hints Grounding and Layout PCB Design Guidelines for Chip Scale Package Evaluating the AD7490 Performance Outline Dimensions Ordering Guide
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