Datasheet AD9410 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 10-Bit, 210 MSPS ADC |
| Pages / Page | 21 / 5 — AD9410. SWITCHING SPECIFICATIONS. Table 2. Parameter. Temp. Test Level. … |
| Revision | A |
| File Format / Size | PDF / 389 Kb |
| Document Language | English |
AD9410. SWITCHING SPECIFICATIONS. Table 2. Parameter. Temp. Test Level. Min. Typ. Max. Unit. DIGITAL SPECIFICATIONS. Table 3. Parameter
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AD9410 SWITCHING SPECIFICATIONS
VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = −0.5 dBFS; clock input = 210 MSPS; TA = 25°C; unless otherwise noted.
Table 2. Parameter Temp Test Level Min Typ Max Unit
SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 210 MSPS Minimum Conversion Rate Full IV 100 MSPS Clock Pulse Width High, tEH 25°C IV 1.2 2.4 ns Clock Pulse Width Low, tEL 25°C IV 1.2 2.4 ns Aperture Delay, tA 25°C V 1.0 ns Aperture Uncertainty (Jitter) 25°C V 0.65 ps rms Output Valid Time, tV Full VI 3.0 ns Output Propagation Delay, tPD Full VI 7.4 ns Output Rise Time, tR 25°C V 1.8 ns Output Fall Time, tF 25°C V 1.4 ns CLKOUT Propagation Delay, t 1 CPD Full VI 2.6 4.8 6.4 ns Data to DCO Skew, (tPD – tCPD) Full IV 0 1 2 ns DS Setup Time, tSDS Full IV 0.5 ns DS Hold Time, tHDS Full IV 0 ns Interleaved Mode (A, B Latency) Full VI A = 6, B = 6 Cycles Parallel Mode (A, B Latency) Full VI A = 7, B = 6 Cycles 1 CLOAD = 5 pF.
DIGITAL SPECIFICATIONS
VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = −0.5 dBFS; clock input = 210 MSPS; TA = 25°C; unless otherwise noted.
Table 3. Parameter Temp Test Level Min Typ Max Unit
DIGITAL INPUTS DFS, Input Logic 1 Voltage Full IV 4 V DFS, Input Logic 0 Voltage Full IV 1 V DFS, Input Logic 1 Current Full V 50 μA DFS, Input Logic 0 Current Full V 50 μA I/P Input Logic 1 Current1 Full V 400 μA I/P Input Logic 0 Current1 Full V 1 μA CLK+, CLK− Differential Input Voltage Full IV 0.4 V CLK+, CLK− Differential Input Resistance Full V 1.6 kΩ CLK+, CLK− Common-Mode Input Voltage2 Full V 1.5 V DS, DS Differential Input Voltage Full IV 0.4 V DS, DS Common-Mode Input Voltage Full V 1.5 V Digital Input Pin Capacitance 25°C V 3 pF DIGITAL OUTPUTS Logic 1 Voltage (VDD = 3.3 V) Full VI VDD – 0.05 V Logic 0 Voltage (VDD = 3.3 V) Full VI 0.05 V Output Coding Binary or Twos Complement 1 I/P pin Logic 1 = 5 V, Logic 0 = GND. It is recommended to use a series 2.5 kΩ (±10%) resistor to VDD when setting to Logic 1 to limit input current. 2 See Clock Input section. Rev. A | Page 4 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS SWITCHING SPECIFICATIONS DIGITAL SPECIFICATIONS AC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLAINATION OF TEST LEVELS Test Level ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION USING THE AD9410 Clock Input ANALOG INPUT DIGITAL OUTPUTS CLOCK OUTPUTS (DCO, ) VOLTAGE REFERENCE TIMING DATA SYNC (DS) OUTLINE DIMENSIONS ORDERING GUIDE
AD9410 SWITCHING SPECIFICATIONS
VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = −0.5 dBFS; clock input = 210 MSPS; TA = 25°C; unless otherwise noted.
Table 2. Parameter Temp Test Level Min Typ Max Unit
SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 210 MSPS Minimum Conversion Rate Full IV 100 MSPS Clock Pulse Width High, tEH 25°C IV 1.2 2.4 ns Clock Pulse Width Low, tEL 25°C IV 1.2 2.4 ns Aperture Delay, tA 25°C V 1.0 ns Aperture Uncertainty (Jitter) 25°C V 0.65 ps rms Output Valid Time, tV Full VI 3.0 ns Output Propagation Delay, tPD Full VI 7.4 ns Output Rise Time, tR 25°C V 1.8 ns Output Fall Time, tF 25°C V 1.4 ns CLKOUT Propagation Delay, t 1 CPD Full VI 2.6 4.8 6.4 ns Data to DCO Skew, (tPD – tCPD) Full IV 0 1 2 ns DS Setup Time, tSDS Full IV 0.5 ns DS Hold Time, tHDS Full IV 0 ns Interleaved Mode (A, B Latency) Full VI A = 6, B = 6 Cycles Parallel Mode (A, B Latency) Full VI A = 7, B = 6 Cycles 1 CLOAD = 5 pF.
DIGITAL SPECIFICATIONS
VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = −0.5 dBFS; clock input = 210 MSPS; TA = 25°C; unless otherwise noted.
Table 3. Parameter Temp Test Level Min Typ Max Unit
DIGITAL INPUTS DFS, Input Logic 1 Voltage Full IV 4 V DFS, Input Logic 0 Voltage Full IV 1 V DFS, Input Logic 1 Current Full V 50 μA DFS, Input Logic 0 Current Full V 50 μA I/P Input Logic 1 Current1 Full V 400 μA I/P Input Logic 0 Current1 Full V 1 μA CLK+, CLK− Differential Input Voltage Full IV 0.4 V CLK+, CLK− Differential Input Resistance Full V 1.6 kΩ CLK+, CLK− Common-Mode Input Voltage2 Full V 1.5 V DS, DS Differential Input Voltage Full IV 0.4 V DS, DS Common-Mode Input Voltage Full V 1.5 V Digital Input Pin Capacitance 25°C V 3 pF DIGITAL OUTPUTS Logic 1 Voltage (VDD = 3.3 V) Full VI VDD – 0.05 V Logic 0 Voltage (VDD = 3.3 V) Full VI 0.05 V Output Coding Binary or Twos Complement 1 I/P pin Logic 1 = 5 V, Logic 0 = GND. It is recommended to use a series 2.5 kΩ (±10%) resistor to VDD when setting to Logic 1 to limit input current. 2 See Clock Input section. Rev. A | Page 4 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS SWITCHING SPECIFICATIONS DIGITAL SPECIFICATIONS AC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLAINATION OF TEST LEVELS Test Level ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION USING THE AD9410 Clock Input ANALOG INPUT DIGITAL OUTPUTS CLOCK OUTPUTS (DCO, ) VOLTAGE REFERENCE TIMING DATA SYNC (DS) OUTLINE DIMENSIONS ORDERING GUIDE
