AD9410SAMPLE N+3SAMPLE N–1 SAMPLE NSAMPLE N+4 SAMPLE N+5AINtASAMPLE N–2SAMPLE N+1 SAMPLE N+2SAMPLE N+6tEHtEL1/fSCLK+CLK–tSDStHDSDSDStPDtVINTERLEAVED DATA OUTPORT ASTATICINVALIDINVALIDINVALIDDATA N+1DATA N+3D7 TO D0PORT BSTATICINVALIDINVALIDINVALIDDATA NDATA N+2D7 TO D0PARALLEL DATA OUTPORT ASTATICINVALIDINVALIDINVALIDINVALIDDATA N+1D7 TO D0PORT BSTATICINVALIDINVALIDINVALIDDATA NDATA N+2D7 TO D0tCPDDCO 2 00 STATIC 9- 67 DCO 01 Figure 2. Timing Diagram Rev. A | Page 6 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS SWITCHING SPECIFICATIONS DIGITAL SPECIFICATIONS AC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLAINATION OF TEST LEVELS Test Level ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION USING THE AD9410 Clock Input ANALOG INPUT DIGITAL OUTPUTS CLOCK OUTPUTS (DCO, ) VOLTAGE REFERENCE TIMING DATA SYNC (DS) OUTLINE DIMENSIONS ORDERING GUIDE