Datasheet MCP6V71, MCP6V71U, MCP6V72, MCP6V74 (Microchip) - 10

MCP6V71/1U/2/4 Note:
Unless otherwise indicated, TA = +25°C, VDD = +2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF.
2.2 Other DC Voltages and Currents 0.7 40 0.6 1 Wafer Lot T = +125°C A 30 T = +85°C 0.5 A ltage T = +25°C A o 0.4 Upper (V – V ) CMH DD 20 T = -40°C A 0.3 10 0.2 0 0.1 (mA) 0.0 -10 Headroom (V) -0.1 -20 T = +125°C A T = +85°C -0.2 A -30 T = +25°C A -0.3 Lower (V – V ) CML SS T = -40°C Input Common Mode V A -0.4 Output Short Circuit Current -40 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) Power Supply Voltage (V) FIGURE 2-19:
Input Common Mode
FIGURE 2-22:
Output Short Circuit Current Voltage Headroom (Range) vs. Ambient vs. Power Supply Voltage. Temperature.
1000 200 180 V = 2V 160 DD 140 100 V -V DD OH 120 100 V = 5.5V T = +125°C DD A ltage Headroom (mV) 80 T = +85°C A o 10 T = +25°C (µA/Amplifier) 60 A T = -40°C A Quiescent Current 40 V -V OL SS 20 Output V 1 0 0.1 1 10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 Output Current Magnitude (mA) Power Supply Voltage (V) FIGURE 2-20:
Output Voltage Headroom
FIGURE 2-23:
Supply Current vs. Power vs. Output Current. Supply Voltage.
100% 90 R = 2 kΩ 90% L 800 Samples (mV) 80 V - V 1 Wafer Lot DD OH 80% 70 70% T = +25ºC A 60 V = 5.5V 60% DD 50 Occurences 50% 40 V - V OL SS 40% 30 30% oltage Headroom 20 20% V = 2V 10 DD 10% V - V DD OH Output V Percentage of 0% 0 -50 -25 0 25 50 75 100 125 0.9 1.2 1.6 1.04 1.08 1.12 1.16 1.24 1.28 1.32 Ambient Temperature (°C) POR Trip Voltage (V) FIGURE 2-21:
Output Voltage Headroom
FIGURE 2-24:
Power-On Reset Trip vs. Ambient Temperature. Voltage. DS20005385B-page 10  2015 Microchip Technology Inc. Document Outline Features Typical Applications Design Aids Related Parts Description Package Types Typical Application Circuit 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Specifications TABLE 1-1: DC Electrical Specifications (Continued) TABLE 1-2: AC Electrical Specifications TABLE 1-3: Temperature Specifications 1.3 Timing Diagrams FIGURE 1-1: Amplifier Start Up. FIGURE 1-2: Offset Correction Settling Time. FIGURE 1-3: Output Overdrive Recovery. 1.4 Test Circuits FIGURE 1-4: AC and DC Test Circuit for Most Noninverting Gain Conditions. FIGURE 1-5: AC and DC Test Circuit for Most Inverting Gain Conditions. FIGURE 1-6: Test Circuit for Dynamic Input Behavior. 2.0 Typical Performance Curves 2.1 DC Input Precision FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage Quadratic Temp. Co. FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage with VCM = VCML. FIGURE 2-5: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMH. FIGURE 2-6: Input Offset Voltage vs. Output Voltage with VDD = 2.0V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage with VDD = 5.5V. FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 2V. FIGURE 2-9: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V. FIGURE 2-10: Common Mode Rejection Ratio. FIGURE 2-11: Power Supply Rejection Ratio. FIGURE 2-12: DC Open-Loop Gain. FIGURE 2-13: CMRR and PSRR vs. Ambient Temperature. FIGURE 2-14: DC Open-Loop Gain vs. Ambient Temperature. FIGURE 2-15: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85°C. FIGURE 2-16: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125°C. FIGURE 2-17: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V. FIGURE 2-18: Input Bias Current vs. Input Voltage (below VSS). 2.2 Other DC Voltages and Currents FIGURE 2-19: Input Common Mode Voltage Headroom (Range) vs. Ambient Temperature. FIGURE 2-20: Output Voltage Headroom vs. Output Current. FIGURE 2-21: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-22: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-23: Supply Current vs. Power Supply Voltage. FIGURE 2-24: Power-On Reset Trip Voltage. FIGURE 2-25: Power-On Reset Voltage vs. Ambient Temperature. 2.3 Frequency Response FIGURE 2-26: CMRR and PSRR vs. Frequency. FIGURE 2-27: Open-Loop Gain vs. Frequency with VDD = 2V. FIGURE 2-28: Open-Loop Gain vs. Frequency with VDD = 5.5V. FIGURE 2-29: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature. FIGURE 2-30: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage. FIGURE 2-31: Gain Bandwidth Product and Phase Margin vs. Output Voltage. FIGURE 2-32: Closed-Loop Output Impedance vs. Frequency with VDD = 2V. FIGURE 2-33: Closed-Loop Output Impedance vs. Frequency with VDD = 5.5V. FIGURE 2-34: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-35: EMIRR vs Frequency. FIGURE 2-36: EMIRR vs RF Input Peak Voltage. FIGURE 2-37: Channel-to-Channel Separation vs. Frequency. 2.4 Input Noise and Distortion FIGURE 2-38: Input Noise Voltage Density and Integrated Input Noise Voltage vs. Frequency. FIGURE 2-39: Input Noise Voltage Density vs. Input Common Mode Voltage. FIGURE 2-40: Intermodulation Distortion vs. Frequency with VCM Disturbance (see Figure 1-6). FIGURE 2-41: Intermodulation Distortion vs. Frequency with VDD Disturbance (see Figure 1-6). FIGURE 2-42: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD = 2V. FIGURE 2-43: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD = 5.5V. 2.5 Time Response FIGURE 2-44: Input Offset Voltage vs. Time with Temperature Change. FIGURE 2-45: Input Offset Voltage vs. Time at Power-Up. FIGURE 2-46: The MCP6V71/1U/2/4 Family Shows No Input Phase Reversal with Overdrive. FIGURE 2-47: Non-inverting Small Signal Step Response. FIGURE 2-48: Non-inverting Large Signal Step Response. FIGURE 2-49: Inverting Small Signal Step Response. FIGURE 2-50: Inverting Large Signal Step Response. FIGURE 2-51: Slew Rate vs. Ambient Temperature. FIGURE 2-52: Output Overdrive Recovery vs. Time with G = -10 V/V. FIGURE 2-53: Output Overdrive Recovery Time vs. Inverting Gain. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) 4.0 Applications 4.1 Overview of Zero-Drift Operation FIGURE 4-1: Simplified Zero-Drift Op Amp Functional Diagram. FIGURE 4-2: First Chopping Clock Phase; Equivalent Amplifier Diagram. FIGURE 4-3: Second Chopping Clock Phase; Equivalent Amplifier Diagram. 4.2 Other Functional Blocks FIGURE 4-4: Simplified Analog Input ESD Structures. FIGURE 4-5: Protecting the Analog Inputs Against High Voltages. FIGURE 4-6: Protecting the Analog Inputs Against High Currents. 4.3 Application Tips FIGURE 4-7: Output Resistor, RISO, Stabilizes Capacitive Loads. FIGURE 4-8: Recommended RISO values for Capacitive Loads. FIGURE 4-9: Output Load. FIGURE 4-10: Amplifier with Parasitic Capacitance. 4.4 Typical Applications FIGURE 4-11: Simple Design. FIGURE 4-12: RTD Sensor. FIGURE 4-13: Offset Correction. FIGURE 4-14: Precision Comparator. 5.0 Design Aids 5.1 FilterLab® Software 5.2 Microchip Advanced Part Selector (MAPS) 5.3 Analog Demonstration and Evaluation Boards 5.4 Application Notes 6.0 Packaging Information 6.1 Package Marking Information 170 µA, 2 MHz Zero-Drift Op Amps Appendix A: Revision History Revision B (September 2015) Revision A (March 2015) Product Identification System AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Worldwide Sales and Service