Datasheet LTC4300A-3 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | Level Shifting Hot Swappable 2-Wire Bus Buffer with Enable |
| Pages / Page | 14 / 3 — e lecTrical characTerisTics The. denotes the specifications which apply … |
| File Format / Size | PDF / 216 Kb |
| Document Language | English |
e lecTrical characTerisTics The. denotes the specifications which apply over the full operating
Model Line for this Datasheet
- LTC4300A-3CDD#PBF LTC4300A-3CDD#PBF LTC4300A-3CDD#TRPBF LTC4300A-3CDD#TRPBF LTC4300A-3CMS8#PBF LTC4300A-3CMS8#PBF LTC4300A-3CMS8#TRPBF LTC4300A-3CMS8#TRPBF LTC4300A-3IDD#PBF LTC4300A-3IDD#PBF LTC4300A-3IDD#TRPBF LTC4300A-3IDD#TRPBF LTC4300A-3IMS8#PBF LTC4300A-3IMS8#PBF LTC4300A-3IMS8#TRPBF LTC4300A-3IMS8#TRPBF
Text Version of Document
LTC4300A-3
e lecTrical characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC2 = 2.7V to 5.5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply
VCC Positive Supply Voltage l 2.7 5.5 V VCC2 Card Side Supply Voltage l 2.7 5.5 V ISD Supply Current in Shutdown Mode VENABLE = 0V 20 µA IVCC1 VCC Supply Current VSDAIN = VSCLIN = 0V, VCC1 = VCC2 = 5.5V 3 4.1 mA IVCC2 VCC2 Supply Current VSDAOUT = VSCLOUT = 0V, VCC1 = VCC2 = 5.5V 2.1 2.9 mA
Start-Up Circuitry
VPRE Precharge Voltage SDA, SCL Floating l 0.8 1.0 1.2 V tIDLE Bus Idle Time l 50 95 150 µs VEN ENABLE Threshold Voltage 0.5 • VCC 0.9 • VCC V VDIS Disable Threshold Voltage ENABLE Pin 0.1 • VCC 0.5 • VCC V IEN ENABLE Input Current ENABLE from 0V to VCC ±0.1 ±1 µA tPHL ENABLE Delay, On-Off 10 ns tPLH ENABLE Delay, Off-On 95 µs
Rise Time Accelerators
IPULLUPAC Transient Boosted Pull-Up Current Positive Transition on SDA, SCL, VCC = 2.7V, 1 2 mA VCC2 = 2.7V, Slew Rate = 1.25V/µs (Note 2)
Input-Output Connection
VOS Input-Output Offset Voltage 10k to VCC on SDA, SCL, VCC = 3.3V (Note 3), l 0 100 175 mV VCC2 = 3.3V, VIN = 0.2V fSCL, SDA Operating Frequency Guaranteed by Design, Not Subject to Test 0 400 kHz CIN Digital Input Capacitance Guaranteed by Design, Not Subject to Test 10 pF VOL Output Low Voltage, Input = 0V SDA, SCL Pins, ISINK = 3mA, VCC = 2.7V, l 0 0.4 V VCC2 = 2.7V ILEAK Input Leakage Current SDA, SCL Pins = VCC = 5.5V, VCC2 = 5.5V ±5 µA
Timing Characteristics
fI2C I2C Operating Frequency (Note 4) 0 400 kHz tBUF Bus Free Time Between Stop and (Note 4) 1.3 µs Start Condition thD,STA Hold Time After (Repeated) Start (Note 4) 0.6 µs Condition tsu,STA Repeated Start Condition Setup Time (Note 4) 0.6 µs tsu,STO Stop Condition Setup Time (Note 4) 0.6 µs thD, DAT Data Hold Time (Note 4) 300 ns tsu, DAT Data Setup Time (Note 4) 100 ns tLOW Clock Low Period (Note 4) 1.3 µs tHIGH Clock High Period (Note 4) 0.6 µs tf Clock, Data Fall Time (Notes 4, 5) 20 + 0.1 • CB 300 ns tr Clock, Data Rise Time (Notes 4, 5) 20 + 0.1 • CB 300 ns tPHL,SKEW High-to-Low Propagation Delay VCC = 2.7V, VCC2 = 5.5V; l 0 ±75 ns Skew, SCL-SDA VCC = 5.5V, VCC2 = 2.7V (Note 6) 4300a3fa 3 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Related Parts Typical Application
e lecTrical characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC2 = 2.7V to 5.5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply
VCC Positive Supply Voltage l 2.7 5.5 V VCC2 Card Side Supply Voltage l 2.7 5.5 V ISD Supply Current in Shutdown Mode VENABLE = 0V 20 µA IVCC1 VCC Supply Current VSDAIN = VSCLIN = 0V, VCC1 = VCC2 = 5.5V 3 4.1 mA IVCC2 VCC2 Supply Current VSDAOUT = VSCLOUT = 0V, VCC1 = VCC2 = 5.5V 2.1 2.9 mA
Start-Up Circuitry
VPRE Precharge Voltage SDA, SCL Floating l 0.8 1.0 1.2 V tIDLE Bus Idle Time l 50 95 150 µs VEN ENABLE Threshold Voltage 0.5 • VCC 0.9 • VCC V VDIS Disable Threshold Voltage ENABLE Pin 0.1 • VCC 0.5 • VCC V IEN ENABLE Input Current ENABLE from 0V to VCC ±0.1 ±1 µA tPHL ENABLE Delay, On-Off 10 ns tPLH ENABLE Delay, Off-On 95 µs
Rise Time Accelerators
IPULLUPAC Transient Boosted Pull-Up Current Positive Transition on SDA, SCL, VCC = 2.7V, 1 2 mA VCC2 = 2.7V, Slew Rate = 1.25V/µs (Note 2)
Input-Output Connection
VOS Input-Output Offset Voltage 10k to VCC on SDA, SCL, VCC = 3.3V (Note 3), l 0 100 175 mV VCC2 = 3.3V, VIN = 0.2V fSCL, SDA Operating Frequency Guaranteed by Design, Not Subject to Test 0 400 kHz CIN Digital Input Capacitance Guaranteed by Design, Not Subject to Test 10 pF VOL Output Low Voltage, Input = 0V SDA, SCL Pins, ISINK = 3mA, VCC = 2.7V, l 0 0.4 V VCC2 = 2.7V ILEAK Input Leakage Current SDA, SCL Pins = VCC = 5.5V, VCC2 = 5.5V ±5 µA
Timing Characteristics
fI2C I2C Operating Frequency (Note 4) 0 400 kHz tBUF Bus Free Time Between Stop and (Note 4) 1.3 µs Start Condition thD,STA Hold Time After (Repeated) Start (Note 4) 0.6 µs Condition tsu,STA Repeated Start Condition Setup Time (Note 4) 0.6 µs tsu,STO Stop Condition Setup Time (Note 4) 0.6 µs thD, DAT Data Hold Time (Note 4) 300 ns tsu, DAT Data Setup Time (Note 4) 100 ns tLOW Clock Low Period (Note 4) 1.3 µs tHIGH Clock High Period (Note 4) 0.6 µs tf Clock, Data Fall Time (Notes 4, 5) 20 + 0.1 • CB 300 ns tr Clock, Data Rise Time (Notes 4, 5) 20 + 0.1 • CB 300 ns tPHL,SKEW High-to-Low Propagation Delay VCC = 2.7V, VCC2 = 5.5V; l 0 ±75 ns Skew, SCL-SDA VCC = 5.5V, VCC2 = 2.7V (Note 6) 4300a3fa 3 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Related Parts Typical Application
