Datasheet ADIS16209 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | High Accuracy, Dual-Axis Digital Inclinometer and Accelerometer |
| Pages / Page | 22 / 6 — Data Sheet. ADIS16209. TIMING SPECIFICATIONS. Table 2. Parameter. … |
| Revision | H |
| File Format / Size | PDF / 523 Kb |
| Document Language | English |
Data Sheet. ADIS16209. TIMING SPECIFICATIONS. Table 2. Parameter. Description. Min1. Typ. Max. Unit. TIMING DIAGRAMS. tDATARATE. tSTALL. SCLK
Model Line for this Datasheet
Text Version of Document
Data Sheet ADIS16209 TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, tilt = 0°, unless otherwise noted.
Table 2. Parameter Description Min1 Typ Max Unit
fSCLK Fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 546 Hz)2 0.01 2.5 MHz Normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 482 Hz)2 0.01 1.0 MHz tDATARATE Chip select period, fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 546 Hz)2 32 μs Chip select period, normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 482 Hz)2 42 μs tSTALL Chip select period, fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 546 Hz)2 10 μs Chip select period, normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 482 Hz)2 12 μs tCS Chip select to clock edge 48.8 ns tDAV Data output valid after SCLK edge 100 ns tDSU Data input setup time before SCLK rising edge 24.4 ns tDHD Data input hold time after SCLK rising edge 48.8 ns tDF Data output fall time 5 12.5 ns tDR Data output rise time 5 12.5 ns tSFS CS high after SCLK edge 5 ns 1 Guaranteed by design, not tested. 2 Note that fS means internal sample rate.
TIMING DIAGRAMS tDATARATE tSTALL CS SCLK
002
tSTALL = tDATARATE – 16/fSCLK
07096- Figure 2. SPI Chip Select Timing
CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB t t DSU DHD DIN W/R A6 A5 A4 A3 A2 D2 D1 LSB
003 07096- Figure 3. SPI Timing (Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)
DATA FRAME CS SCLK DIN W/R A6 A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
004
WRITE = 1 REGISTER ADDRESS DATA FOR WRITE COMMANDS READ = 0 DON’T CARE FOR READ COMMANDS
07096- Figure 4. DIN Bit Sequence Rev. F | Page 5 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RECOMMENDED PAD GEOMETRY TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC OPERATION OUTPUT DATA REGISTERS Accelerometers Horizontal Incline Angle Vertical Incline Angle Internal Temperature Power Supply Auxiliary ADC OPERATION CONTROL REGISTERS Internal Sample Rate Power Management Digital Filtering Digital I/O Lines Data-Ready I/O Indicator Self-Test General-Purpose I/O Auxiliary DAC Global Commands CALIBRATION REGISTERS ALARM REGISTERS Status APPLICATIONS INFORMATION POWER SUPPLY CONSIDERATIONS Power-On-Reset Function Transient Current from VDD Ramp Rate Filter Settling ASSEMBLY INTERFACE BOARD OUTLINE DIMENSIONS ORDERING GUIDE
TA = 25°C, VDD = 3.3 V, tilt = 0°, unless otherwise noted.
Table 2. Parameter Description Min1 Typ Max Unit
fSCLK Fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 546 Hz)2 0.01 2.5 MHz Normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 482 Hz)2 0.01 1.0 MHz tDATARATE Chip select period, fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 546 Hz)2 32 μs Chip select period, normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 482 Hz)2 42 μs tSTALL Chip select period, fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 546 Hz)2 10 μs Chip select period, normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 482 Hz)2 12 μs tCS Chip select to clock edge 48.8 ns tDAV Data output valid after SCLK edge 100 ns tDSU Data input setup time before SCLK rising edge 24.4 ns tDHD Data input hold time after SCLK rising edge 48.8 ns tDF Data output fall time 5 12.5 ns tDR Data output rise time 5 12.5 ns tSFS CS high after SCLK edge 5 ns 1 Guaranteed by design, not tested. 2 Note that fS means internal sample rate.
TIMING DIAGRAMS tDATARATE tSTALL CS SCLK
002
tSTALL = tDATARATE – 16/fSCLK
07096- Figure 2. SPI Chip Select Timing
CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB t t DSU DHD DIN W/R A6 A5 A4 A3 A2 D2 D1 LSB
003 07096- Figure 3. SPI Timing (Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)
DATA FRAME CS SCLK DIN W/R A6 A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
004
WRITE = 1 REGISTER ADDRESS DATA FOR WRITE COMMANDS READ = 0 DON’T CARE FOR READ COMMANDS
07096- Figure 4. DIN Bit Sequence Rev. F | Page 5 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RECOMMENDED PAD GEOMETRY TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC OPERATION OUTPUT DATA REGISTERS Accelerometers Horizontal Incline Angle Vertical Incline Angle Internal Temperature Power Supply Auxiliary ADC OPERATION CONTROL REGISTERS Internal Sample Rate Power Management Digital Filtering Digital I/O Lines Data-Ready I/O Indicator Self-Test General-Purpose I/O Auxiliary DAC Global Commands CALIBRATION REGISTERS ALARM REGISTERS Status APPLICATIONS INFORMATION POWER SUPPLY CONSIDERATIONS Power-On-Reset Function Transient Current from VDD Ramp Rate Filter Settling ASSEMBLY INTERFACE BOARD OUTLINE DIMENSIONS ORDERING GUIDE
