Preliminary Datasheet ADAR1000 (Analog Devices) - 5

Preliminary Technical Data ADAR1000 Parameter Min Typ. Max Meas. Unit Condition
LOGIC OUTPUTS SDO, SDIO VOH, Output High Voltage 1.4 V IOH=TBD mA VOL, Output Low Voltage 0.4 V IOL=TBD mA IOH TBD µA IOL TBD µA POWER SUPPLIES AVDD1 -5.25 -5.0 -4.75 V AVVD3 3.135 3.3 3.465 V IAVDD1 TBD 2 mA LNA & PA bias outputs unloaded IAVDD3 Reset (standby) 30 26 mA TX Channel 113 88 mA per channel, increased from standby current TX Channel 50% Bias Setting TBD mA as above RX Channel 87 60 mA as above RX Channel 50% Bias Setting TBD mA as above Notes: 1 Nominal Bias Register settings: Reg0x034=0x05, Reg0x035=0x3D, Reg0x036=0x3D, Reg0x37=0x05 2 T(OC) = Offset + Scale * ADC value Rev. PrF| Page 5 of 51 Document Outline Features Applications General Description Functional Block Diagram Specifications Timing Specifications Timing Diagram SPI Block Write Mode Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Changes from Previous Silicon Revision T/R switch driver output External PA and LNA bias DACs Eliminated the -3.3V supply input to the chip New PA_ON input pin Applications Gain Control Registers Switched Attenuator Control TR_SW_POS and TR_SW_NEG (T/R Switch Control) TX/RX Subcircuit Control TR_SOURCE = 0 SPI Programming Example Register Maps Address: 0x000, Reset: 0x00, Name: INTERFACE_CONFIG_A Outline Dimensions