Preliminary Datasheet ADAR1000 (Analog Devices) - 10

ADAR1000 Preliminary Technical Data
J13 RX1 Channel 1 RX input L1 RX4 Channel 4 RX input L13 TX1 Channel 1 TX output M3 CSB SPI Chip Select CMOS Input. When CSB goes high the data stored in the shift register is loaded into the registers. M4 SDO SPI Data Out CMOS output M5 SDIO SPI Data In CMOS input M6 SCLK SPI Clock CMOS input M8 CREG1 Decoupling capacitor for 1.8V LDO reference M9 CREG2 Decoupling capacitor for 2.8V LDO output M10, M11, N11 AVDD3 3.3V Voltage Power Supply N2 RX_LOAD Load TX registers CMOS input N3 TX_LOAD Load TX registers CMOS input N4 ADDR0 Chip SPI Address CMOS input N5 ADDR1 Chip SPI Address CMOS input N6 TR TX/RX Switch Select CMOS input N9 CREG4 Decoupling capacitor for 1.8V LDO output N10 CREG3 Decoupling capacitor for 2.8V LDO reference N13 DET1 Channel 1 power detector input Rev. PrF | Page 10 of 51 Document Outline Features Applications General Description Functional Block Diagram Specifications Timing Specifications Timing Diagram SPI Block Write Mode Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Changes from Previous Silicon Revision T/R switch driver output External PA and LNA bias DACs Eliminated the -3.3V supply input to the chip New PA_ON input pin Applications Gain Control Registers Switched Attenuator Control TR_SW_POS and TR_SW_NEG (T/R Switch Control) TX/RX Subcircuit Control TR_SOURCE = 0 SPI Programming Example Register Maps Address: 0x000, Reset: 0x00, Name: INTERFACE_CONFIG_A Outline Dimensions