Preliminary Datasheet ADAR1000 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | 4 Channel X/Ku Band Beamformer |
| Pages / Page | 51 / 3 — Preliminary Technical Data. ADAR1000. SPECIFICATIONS. Table 1. Parameter. … |
| Revision | PrF |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
Preliminary Technical Data. ADAR1000. SPECIFICATIONS. Table 1. Parameter. Min. Typ. Max. Meas. Unit. Condition
Text Version of Document
Preliminary Technical Data ADAR1000 SPECIFICATIONS
Unless otherwise noted, AVDD1 = -5 V ± 5%, AVDD3 = 3.3 V ± 5%, GND = 0 V. Power in dBm is referred to 50 Ω, TA = 25OC; device is programmed to max. channel gain and standard bias conditions1.
Table 1. Parameter Min Typ. Max Meas. Unit Condition
OPERATING CONDITIONS Operating Temperature -40 85 RF Frequency Range 8 15 GHz TX SECTION Maximum Gain RF_IO to TX output; same below 9.5 GHz 20 20 dB 11.5 GHz 19 19 Gain Flatness Any 1 GHz between 9 to 14 GHz +/- 1 +/-0.6 dB From 9 to 14 GHz +/- 2 dB From 8 to 15 GHz +/- 3 +/- 2.5 dB Gain Variation over Temperature +/- 3.5 +/- 3 dB OP1dB 11.5 dB Gain Setting 8.5 9 dBm 50% Bias Setting TBD dBm PSAT at 11.5 dB gain 10 11 dBm Gain Adjustment Range 31 >31 dB VGA and Step Attenuator Gain Resolution 0.5 0.5 dB RMS Gain Error TBD dB After Calibration Phase Adjustment Range 360 360 O Phase Resolution < 2.8 2.8 O RMS Phase Error Un-calibrated 5 <2.5 O Calibrated TBD O Noise Figure 27 25 dB max gain dB max gain Channel to Channel Isolation 30 > 40 dB TX Output to Common Port Isolation 50 > 70 dB Output Return Loss -10 -9 dB Input Return Loss -10 -12 dB RF_IO pin RX SECTION Maximum Gain RX Input to RF_IO 9.5 GHz 9 9.5 dB 11.5 GHz 8 8.5 dB Gain Variation over Temperature +/- 3.5 +/- 3 dB Gain Flatness +/- 1 +/- 0.6 dB Over 1GHz Gain Flatness (9 -14 GHz) dB IP1dB (7.5dB Gain Setting) -12 -15 dBm IIP3 (7.5dB Gain Setting) TBD dBm Gain Adjustment Range 31 > 31 dB VGA and Step Attenuator Gain Resolution 0.5 0.5 dB RMS Gain Error TBD dB Phase Adjustment Range 360 360 O Phase Resolution < 2.8 2.8 O RMS Phase Error Rev. PrF| Page 3 of 51 Document Outline Features Applications General Description Functional Block Diagram Specifications Timing Specifications Timing Diagram SPI Block Write Mode Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Changes from Previous Silicon Revision T/R switch driver output External PA and LNA bias DACs Eliminated the -3.3V supply input to the chip New PA_ON input pin Applications Gain Control Registers Switched Attenuator Control TR_SW_POS and TR_SW_NEG (T/R Switch Control) TX/RX Subcircuit Control TR_SOURCE = 0 SPI Programming Example Register Maps Address: 0x000, Reset: 0x00, Name: INTERFACE_CONFIG_A Outline Dimensions
Unless otherwise noted, AVDD1 = -5 V ± 5%, AVDD3 = 3.3 V ± 5%, GND = 0 V. Power in dBm is referred to 50 Ω, TA = 25OC; device is programmed to max. channel gain and standard bias conditions1.
Table 1. Parameter Min Typ. Max Meas. Unit Condition
OPERATING CONDITIONS Operating Temperature -40 85 RF Frequency Range 8 15 GHz TX SECTION Maximum Gain RF_IO to TX output; same below 9.5 GHz 20 20 dB 11.5 GHz 19 19 Gain Flatness Any 1 GHz between 9 to 14 GHz +/- 1 +/-0.6 dB From 9 to 14 GHz +/- 2 dB From 8 to 15 GHz +/- 3 +/- 2.5 dB Gain Variation over Temperature +/- 3.5 +/- 3 dB OP1dB 11.5 dB Gain Setting 8.5 9 dBm 50% Bias Setting TBD dBm PSAT at 11.5 dB gain 10 11 dBm Gain Adjustment Range 31 >31 dB VGA and Step Attenuator Gain Resolution 0.5 0.5 dB RMS Gain Error TBD dB After Calibration Phase Adjustment Range 360 360 O Phase Resolution < 2.8 2.8 O RMS Phase Error Un-calibrated 5 <2.5 O Calibrated TBD O Noise Figure 27 25 dB max gain dB max gain Channel to Channel Isolation 30 > 40 dB TX Output to Common Port Isolation 50 > 70 dB Output Return Loss -10 -9 dB Input Return Loss -10 -12 dB RF_IO pin RX SECTION Maximum Gain RX Input to RF_IO 9.5 GHz 9 9.5 dB 11.5 GHz 8 8.5 dB Gain Variation over Temperature +/- 3.5 +/- 3 dB Gain Flatness +/- 1 +/- 0.6 dB Over 1GHz Gain Flatness (9 -14 GHz) dB IP1dB (7.5dB Gain Setting) -12 -15 dBm IIP3 (7.5dB Gain Setting) TBD dBm Gain Adjustment Range 31 > 31 dB VGA and Step Attenuator Gain Resolution 0.5 0.5 dB RMS Gain Error TBD dB Phase Adjustment Range 360 360 O Phase Resolution < 2.8 2.8 O RMS Phase Error Rev. PrF| Page 3 of 51 Document Outline Features Applications General Description Functional Block Diagram Specifications Timing Specifications Timing Diagram SPI Block Write Mode Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Changes from Previous Silicon Revision T/R switch driver output External PA and LNA bias DACs Eliminated the -3.3V supply input to the chip New PA_ON input pin Applications Gain Control Registers Switched Attenuator Control TR_SW_POS and TR_SW_NEG (T/R Switch Control) TX/RX Subcircuit Control TR_SOURCE = 0 SPI Programming Example Register Maps Address: 0x000, Reset: 0x00, Name: INTERFACE_CONFIG_A Outline Dimensions
