Datasheet LT1977 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | High Voltage 1.5A, 500kHz Step-Down Switching Regulator with 100µA Quiescent Current |
| Pages / Page | 24 / 6 — TYPICAL PERFOR A CE CHARACTERISTICS. Dropout Operation. Burst Mode … |
| File Format / Size | PDF / 334 Kb |
| Document Language | English |
TYPICAL PERFOR A CE CHARACTERISTICS. Dropout Operation. Burst Mode Operation. No Load 1A Step Response. Step Response
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Text Version of Document
LT1977
W U TYPICAL PERFOR A CE CHARACTERISTICS Dropout Operation Dropout Operation Burst Mode Operation
4.0 V 6 OUT = 3.3V VOUT = 5V BOOST DIODE = DIODES INC B1100 3.5 BOOST DIODE = DIODES INC B1100 5 3.0 LOAD CURRENT = 250mA VOUT LOAD CURRENT = 250mA 20mV/DIV 4 2.5 2.0 LOAD CURRENT = 1.25A 3 ISW LOAD CURRENT = 1.25mA 1.5 500mA/DIV 2 OUTPUT VOLTAGE (V) 1.0 OUTPUT VOLTAGE (V) 1 VIN = 12V 5ms/DIV 1977 G14 0.5 VOUT = 3.3V IQ = 100µA 0 0 2 2.5 3 3.5 4 4.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 INPUT VOLTAGE (V) INPUT VOLTAGE (V) 1977 G23
Burst Mode Operation No Load 1A Step Response
1977 G24
Step Response
V V V OUT OUT OUT 50mV/DIV 50mV/DIV 20mV/DIV IOUT 500mA/DIV I I SW OUT 500mA/DIV 500mA/DIV V V 500µs/DIV 1977 G17 V 500µs/DIV 1977 G18 IN = 12V 2µs/DIV 1977 G15 IN = 12V IN = 12V V V V OUT = 3.3V OUT = 3.3V OUT = 3.3V I C C Q = 100µA OUT = 100µF OUT = 100µF IDC = 0mA IDC = 350mA
U U U PI FU CTIO S NC (Pins 1, 3, 5):
No Connection.
BOOST (Pin 6):
The BOOST pin is used to provide a drive voltage, higher than the input voltage, to the internal
SW (Pin 2):
The SW pin is the emitter of the on-chip power bipolar NPN power switch. Without this added voltage, the NPN switch. This pin is driven up to the input pin voltage typical switch voltage loss would be about 1.5V. The during switch on time. Inductor current drives the SW pin additional BOOST voltage allows the switch to saturate negative during switch off time. Negative voltage is clamped and its voltage loss approximates that of a 0.2Ω FET with the external catch diode. Maximum negative switch structure. voltage allowed is –0.8V.
C V T (Pin 7):
A capacitor on the CT pin determines the amount
IN (Pin 4):
This is the collector of the on-chip power NPN of delay time between the PGFB pin exceeding its thresh- switch. VIN powers the internal control circuitry when a old (V voltage on the BIAS pin is not present. High di/dt edges PGFB) and the PG pin set to a high impedance state. When the PGFB pin rises above V occur on this pin during switch turn on and off. Keep the PGFB, current is sourced from the C path short from the V T pin into the external capacitor. When the volt- IN pin through the input bypass age on the external capacitor reaches an internal clamp capacitor, through the catch diode back to SW. All trace (V inductance on this path will create a voltage spike at switch CT), the PG pin becomes a high impedance node. The resultant PG delay time is given by t = C off, adding to the V CT • VCT/ICT. If the CE voltage across the internal NPN. 1977fa 6
W U TYPICAL PERFOR A CE CHARACTERISTICS Dropout Operation Dropout Operation Burst Mode Operation
4.0 V 6 OUT = 3.3V VOUT = 5V BOOST DIODE = DIODES INC B1100 3.5 BOOST DIODE = DIODES INC B1100 5 3.0 LOAD CURRENT = 250mA VOUT LOAD CURRENT = 250mA 20mV/DIV 4 2.5 2.0 LOAD CURRENT = 1.25A 3 ISW LOAD CURRENT = 1.25mA 1.5 500mA/DIV 2 OUTPUT VOLTAGE (V) 1.0 OUTPUT VOLTAGE (V) 1 VIN = 12V 5ms/DIV 1977 G14 0.5 VOUT = 3.3V IQ = 100µA 0 0 2 2.5 3 3.5 4 4.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 INPUT VOLTAGE (V) INPUT VOLTAGE (V) 1977 G23
Burst Mode Operation No Load 1A Step Response
1977 G24
Step Response
V V V OUT OUT OUT 50mV/DIV 50mV/DIV 20mV/DIV IOUT 500mA/DIV I I SW OUT 500mA/DIV 500mA/DIV V V 500µs/DIV 1977 G17 V 500µs/DIV 1977 G18 IN = 12V 2µs/DIV 1977 G15 IN = 12V IN = 12V V V V OUT = 3.3V OUT = 3.3V OUT = 3.3V I C C Q = 100µA OUT = 100µF OUT = 100µF IDC = 0mA IDC = 350mA
U U U PI FU CTIO S NC (Pins 1, 3, 5):
No Connection.
BOOST (Pin 6):
The BOOST pin is used to provide a drive voltage, higher than the input voltage, to the internal
SW (Pin 2):
The SW pin is the emitter of the on-chip power bipolar NPN power switch. Without this added voltage, the NPN switch. This pin is driven up to the input pin voltage typical switch voltage loss would be about 1.5V. The during switch on time. Inductor current drives the SW pin additional BOOST voltage allows the switch to saturate negative during switch off time. Negative voltage is clamped and its voltage loss approximates that of a 0.2Ω FET with the external catch diode. Maximum negative switch structure. voltage allowed is –0.8V.
C V T (Pin 7):
A capacitor on the CT pin determines the amount
IN (Pin 4):
This is the collector of the on-chip power NPN of delay time between the PGFB pin exceeding its thresh- switch. VIN powers the internal control circuitry when a old (V voltage on the BIAS pin is not present. High di/dt edges PGFB) and the PG pin set to a high impedance state. When the PGFB pin rises above V occur on this pin during switch turn on and off. Keep the PGFB, current is sourced from the C path short from the V T pin into the external capacitor. When the volt- IN pin through the input bypass age on the external capacitor reaches an internal clamp capacitor, through the catch diode back to SW. All trace (V inductance on this path will create a voltage spike at switch CT), the PG pin becomes a high impedance node. The resultant PG delay time is given by t = C off, adding to the V CT • VCT/ICT. If the CE voltage across the internal NPN. 1977fa 6
