Datasheet LT1977 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | High Voltage 1.5A, 500kHz Step-Down Switching Regulator with 100µA Quiescent Current |
| Pages / Page | 24 / 7 — PI FU CTIO S. FB (Pin 12):. GND (Pins 8, 17):. PGFB (PIN 13):. CSS (Pin … |
| File Format / Size | PDF / 334 Kb |
| Document Language | English |
PI FU CTIO S. FB (Pin 12):. GND (Pins 8, 17):. PGFB (PIN 13):. CSS (Pin 9):. SYNC (Pin 14):. BIAS (Pin 10):. SHDN (Pin 15):
Model Line for this Datasheet
Text Version of Document
LT1977
U U U PI FU CTIO S
voltage on the PGFB pin drops below VPGFB, CCT will be During the sleep portion of Burst Mode operation, the VC discharged rapidly to 0V and PG will be active low with a pin is held at a voltage slightly below the burst threshold 200µA sink capability. If the CT pin is clamped (Power Good for better transient response. Driving the VC pin to ground condition) during normal operation and SHDN is taken low, will disable switching and place the IC into sleep mode. the CT pin will be discharged and a delay period will occur
FB (Pin 12):
The feedback pin is used to determine the when SHDN is returned high. See the Power Good section output voltage using an external voltage divider from the in Applications Information for details. output that generates 1.25V at the FB pin . When the FB pin
GND (Pins 8, 17):
The GND pin connection acts as the drops below 0.9V, switching frequency is reduced, the reference for the regulated output, so load regulation will SYNC function is disabled and output ramp rate control is suffer if the “ground” end of the load is not at the same enabled via the CSS pin. See the Feedback section in voltage as the GND pin of the IC. This condition will occur Applications Information for details. when load current or other currents flow through metal
PGFB (PIN 13):
The PGFB pin is the positive input to a paths between the GND pin and the load ground. Keep the comparator whose negative input is set at V path between the GND pin and the load ground short and PGFB. When PGFB is taken above V use a ground plane when possible. The GND pin also acts PGFB, current (ICSS) is sourced into the C as a heat sink and should be soldered (along with the T pin starting the PG delay period. When the voltage on the PGFB pin drops below V exposed leadframe) to the copper ground plane to reduce PGFB, the CT pin is rapidly discharged resetting the PG delay period. The PGFB volt- thermal resistance (see Applications Information). age is typically generated by a resistive divider from the
CSS (Pin 9):
A capacitor from the CSS pin to the regulated regulated output or input supply. See Power Good section output voltage determines the output voltage ramp rate in Applications Information for details. during start-up. When the current through the CSS capaci-
SYNC (Pin 14):
The SYNC pin is used to synchronize the tor exceeds the CSS threshold (ICSS), the voltage ramp of internal oscillator to an external signal. It is directly logic the output is limited. The CSS threshold is proportional to compatible and can be driven with any signal between the FB voltage (see Typical Performance Characteristics) 30% and 70% duty cycle. The synchronizing range is and is defeated for FB voltage greater than 0.9V (typical). equal to maximum initial operating frequency up to 700kHz. See Soft-Start section in Applications Information for When the voltage on the FB pin is below 0.9V the SYNC details. function is disabled. See the Synchronizing section in
BIAS (Pin 10):
The BIAS pin is used to improve efficiency Applications Information for details. when operating at higher input voltages and light load
SHDN (Pin 15):
The SHDN pin is used to turn off the current. Connecting this pin to the regulated output volt- regulator and to reduce input current to less than 1µA. The age forces most of the internal circuitry to draw its SHDN pin requires a voltage above 1.3V with a typical operating current from the output voltage rather than the source current of 5µA to take the IC out of the shutdown input supply. This architecture increases efficiency espe- state. cially when the input voltage is much higher than the output. Minimum output voltage setting for this mode of
PG (Pin 16):
The PG pin is functional only when the SHDN operation is 3V. pin is above its threshold, and is active low when the internal clamp on the C
V
T pin is below its clamp level and
C (Pin 11):
The VC pin is the output of the error amplifier high impedance when the clamp is active. The PG pin has and the input of the peak switch current comparator. It is a typical sink capability of 200µA. See the Power Good normally used for frequency compensation, but can also section in Applications Information for details. serve as a current clamp or control loop override. VC sits at about 0.45V for light loads and 2.2V at maximum load. 1977fa 7
U U U PI FU CTIO S
voltage on the PGFB pin drops below VPGFB, CCT will be During the sleep portion of Burst Mode operation, the VC discharged rapidly to 0V and PG will be active low with a pin is held at a voltage slightly below the burst threshold 200µA sink capability. If the CT pin is clamped (Power Good for better transient response. Driving the VC pin to ground condition) during normal operation and SHDN is taken low, will disable switching and place the IC into sleep mode. the CT pin will be discharged and a delay period will occur
FB (Pin 12):
The feedback pin is used to determine the when SHDN is returned high. See the Power Good section output voltage using an external voltage divider from the in Applications Information for details. output that generates 1.25V at the FB pin . When the FB pin
GND (Pins 8, 17):
The GND pin connection acts as the drops below 0.9V, switching frequency is reduced, the reference for the regulated output, so load regulation will SYNC function is disabled and output ramp rate control is suffer if the “ground” end of the load is not at the same enabled via the CSS pin. See the Feedback section in voltage as the GND pin of the IC. This condition will occur Applications Information for details. when load current or other currents flow through metal
PGFB (PIN 13):
The PGFB pin is the positive input to a paths between the GND pin and the load ground. Keep the comparator whose negative input is set at V path between the GND pin and the load ground short and PGFB. When PGFB is taken above V use a ground plane when possible. The GND pin also acts PGFB, current (ICSS) is sourced into the C as a heat sink and should be soldered (along with the T pin starting the PG delay period. When the voltage on the PGFB pin drops below V exposed leadframe) to the copper ground plane to reduce PGFB, the CT pin is rapidly discharged resetting the PG delay period. The PGFB volt- thermal resistance (see Applications Information). age is typically generated by a resistive divider from the
CSS (Pin 9):
A capacitor from the CSS pin to the regulated regulated output or input supply. See Power Good section output voltage determines the output voltage ramp rate in Applications Information for details. during start-up. When the current through the CSS capaci-
SYNC (Pin 14):
The SYNC pin is used to synchronize the tor exceeds the CSS threshold (ICSS), the voltage ramp of internal oscillator to an external signal. It is directly logic the output is limited. The CSS threshold is proportional to compatible and can be driven with any signal between the FB voltage (see Typical Performance Characteristics) 30% and 70% duty cycle. The synchronizing range is and is defeated for FB voltage greater than 0.9V (typical). equal to maximum initial operating frequency up to 700kHz. See Soft-Start section in Applications Information for When the voltage on the FB pin is below 0.9V the SYNC details. function is disabled. See the Synchronizing section in
BIAS (Pin 10):
The BIAS pin is used to improve efficiency Applications Information for details. when operating at higher input voltages and light load
SHDN (Pin 15):
The SHDN pin is used to turn off the current. Connecting this pin to the regulated output volt- regulator and to reduce input current to less than 1µA. The age forces most of the internal circuitry to draw its SHDN pin requires a voltage above 1.3V with a typical operating current from the output voltage rather than the source current of 5µA to take the IC out of the shutdown input supply. This architecture increases efficiency espe- state. cially when the input voltage is much higher than the output. Minimum output voltage setting for this mode of
PG (Pin 16):
The PG pin is functional only when the SHDN operation is 3V. pin is above its threshold, and is active low when the internal clamp on the C
V
T pin is below its clamp level and
C (Pin 11):
The VC pin is the output of the error amplifier high impedance when the clamp is active. The PG pin has and the input of the peak switch current comparator. It is a typical sink capability of 200µA. See the Power Good normally used for frequency compensation, but can also section in Applications Information for details. serve as a current clamp or control loop override. VC sits at about 0.45V for light loads and 2.2V at maximum load. 1977fa 7
