Datasheet LT6411 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 650MHz Differential ADC Driver/Dual Selectable Gain Amplifier |
| Pages / Page | 16 / 9 — APPLICATIONS INFORMATION Power Supplies. Do not leave any supply pins … |
| File Format / Size | PDF / 371 Kb |
| Document Language | English |
APPLICATIONS INFORMATION Power Supplies. Do not leave any supply pins disconnected. or the part may not function correctly!
Model Line for this Datasheet
Text Version of Document
LT6411
APPLICATIONS INFORMATION Power Supplies
Since the EN pin is referenced to DGND, it may need to be pulled below ground in those cases. In order to protect the The LT6411 can be operated on as little as ±2.25V or a internal enable circuitry, the EN pin should not be forced single 4.5V supply and as much as ±6V or a single 12V more than 0.5V below DGND. supply. Internally, each supply is independent to improve channel isolation. Note that the Exposed Pad is internally In single supply applications above 5.5V, an additional connected to VEE and must not be grounded when using resistor may be needed from the EN pin to DGND if the split supplies.
Do not leave any supply pins disconnected
pin is ever allowed to fl oat. For example, on a 12V single
or the part may not function correctly!
supply, a 33k resistor would protect the pin from fl oating too high while still allowing the internal pull-up resistor
Enable/Shutdown
to disable the part. The LT6411 has a TTL compatible shutdown mode con- The DGND pin should not be pulled above the EN pin since trolled by the EN pin and referenced to the DGND pin. If doing so will turn on an ESD protection diode. If the EN the amplifi er will be enabled at all times, the EN pin can pin voltage is forced a diode drop below the DGND pin, be connected directly to DGND. If the enable function is current should be limited to 10mA or less. desired, either driving the pin above 2V or allowing the The enable/disable times of the LT6411 are fast when internal 46k pull-up resistor to pull the EN pin to the top driven with a logic input. Turn on (from 50% EN input to rail will disable the amplifi er. When disabled, the DC output 50% output) typically occurs in less than 50ns. Turn off impedance will rise to approximately 740Ω through the is slower, but is less than 300ns. internal feedback and gain resistors (assuming inputs at ground). Supply current into the amplifi er in the disabled
Gain Selection
state will be primarily through VCC and approximately equal to (V The gain of the internal amplifi ers of the LT6411 is confi g- CC – VEN)/46k. ured by connecting the IN+ and IN– pins to the input signal It is important that the two following constraints on the or ground in the combinations shown in Figure 1. DGND pin and the EN pin are always followed: As shown in the Simplifi ed Schematic, the IN– pins connect VCC – VDGND ≥ 3V to the internal gain resistor of each amplifi er, and therefore, –0.5V ≤ VEN – VDGND ≤ 5.5V each pin can be confi gured independently. Floating the Split supplies of ±3V to ±5.5V will satisfy these require- IN– pins is not recommended as the parasitic capacitance ments with DGND connected to 0V. causes an AC gain of 2 at high frequencies, despite a DC gain of +1. Both inputs are connected together in the gain In dual supply cases with VCC less than 3V, DGND should of +1 confi guration to avoid this limitation. be connected to a potential below ground such as VEE. +V +V +V IN+ AV = +1 OUT+ A LT6411 OUT+ V = –1 LT6411 LT6411 OUT– + IN+ + IN+ + – – – AV = +2 IN– – – IN– – OUT+ IN– OUT– OUT– + + + 6411 F01 –V –V –V
Figure 1. LT6411 Confi gured in Noninverting Gain of 2, Noninverting Gain of 1 and Inverting Gain of 1, All Shown with Dual Supplies
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APPLICATIONS INFORMATION Power Supplies
Since the EN pin is referenced to DGND, it may need to be pulled below ground in those cases. In order to protect the The LT6411 can be operated on as little as ±2.25V or a internal enable circuitry, the EN pin should not be forced single 4.5V supply and as much as ±6V or a single 12V more than 0.5V below DGND. supply. Internally, each supply is independent to improve channel isolation. Note that the Exposed Pad is internally In single supply applications above 5.5V, an additional connected to VEE and must not be grounded when using resistor may be needed from the EN pin to DGND if the split supplies.
Do not leave any supply pins disconnected
pin is ever allowed to fl oat. For example, on a 12V single
or the part may not function correctly!
supply, a 33k resistor would protect the pin from fl oating too high while still allowing the internal pull-up resistor
Enable/Shutdown
to disable the part. The LT6411 has a TTL compatible shutdown mode con- The DGND pin should not be pulled above the EN pin since trolled by the EN pin and referenced to the DGND pin. If doing so will turn on an ESD protection diode. If the EN the amplifi er will be enabled at all times, the EN pin can pin voltage is forced a diode drop below the DGND pin, be connected directly to DGND. If the enable function is current should be limited to 10mA or less. desired, either driving the pin above 2V or allowing the The enable/disable times of the LT6411 are fast when internal 46k pull-up resistor to pull the EN pin to the top driven with a logic input. Turn on (from 50% EN input to rail will disable the amplifi er. When disabled, the DC output 50% output) typically occurs in less than 50ns. Turn off impedance will rise to approximately 740Ω through the is slower, but is less than 300ns. internal feedback and gain resistors (assuming inputs at ground). Supply current into the amplifi er in the disabled
Gain Selection
state will be primarily through VCC and approximately equal to (V The gain of the internal amplifi ers of the LT6411 is confi g- CC – VEN)/46k. ured by connecting the IN+ and IN– pins to the input signal It is important that the two following constraints on the or ground in the combinations shown in Figure 1. DGND pin and the EN pin are always followed: As shown in the Simplifi ed Schematic, the IN– pins connect VCC – VDGND ≥ 3V to the internal gain resistor of each amplifi er, and therefore, –0.5V ≤ VEN – VDGND ≤ 5.5V each pin can be confi gured independently. Floating the Split supplies of ±3V to ±5.5V will satisfy these require- IN– pins is not recommended as the parasitic capacitance ments with DGND connected to 0V. causes an AC gain of 2 at high frequencies, despite a DC gain of +1. Both inputs are connected together in the gain In dual supply cases with VCC less than 3V, DGND should of +1 confi guration to avoid this limitation. be connected to a potential below ground such as VEE. +V +V +V IN+ AV = +1 OUT+ A LT6411 OUT+ V = –1 LT6411 LT6411 OUT– + IN+ + IN+ + – – – AV = +2 IN– – – IN– – OUT+ IN– OUT– OUT– + + + 6411 F01 –V –V –V
Figure 1. LT6411 Confi gured in Noninverting Gain of 2, Noninverting Gain of 1 and Inverting Gain of 1, All Shown with Dual Supplies
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