Datasheet ADSP-BF522C, ADSP-BF523C, ADSP-BF524C, ADSP-BF525C, ADSP-BF526C, ADSP-BF527C (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Blackfin Embedded Processor with Codec |
| Pages / Page | 36 / 7 — 1/fS. LEFT CHANNEL. RIGHT CHANNEL. ADCLRC/. DACLRC. CODEC_BCLK. ADCDAT/. … |
| Revision | A |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
1/fS. LEFT CHANNEL. RIGHT CHANNEL. ADCLRC/. DACLRC. CODEC_BCLK. ADCDAT/. DACDAT. X = DON’T CARE
Model Line for this Datasheet
Text Version of Document
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
1/fS LEFT CHANNEL RIGHT CHANNEL ADCLRC/ DACLRC CODEC_BCLK ADCDAT/ X 1 2 3 4 N X X 1 2 3 N X DACDAT X = DON’T CARE.
Figure 8. I2S Audio Input Mode
1/fS LEFT CHANNEL RIGHT CHANNEL ADCLRC/ DACLRC CODEC_BCLK ADCDAT/ 1 2 3 N 1 2 3 N X X X DACDAT X = DON’T CARE.
Figure 9. Frame Sync/PCM Mode Audio Input (Submode 1) [Bit LRP = 0]
1/fS LEFT CHANNEL RIGHT CHANNEL ADCLRC/ DACLRC CODEC_BCLK ADCDAT/ X 1 2 3 N 1 2 3 N X X DACDAT X = DON’T CARE.
Figure 10. Frame Sync/PCM Mode Audio Input (Submode 2) [Bit LRP = 1] Rev. A | Page 7 of 36 | March 2010 Document Outline Blackfin Embedded Processor with Codec Processor Features Embedded Codec Features Peripherals Table of Contents Revision History General Description Codec Description ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Analog Audio Interfaces Stereo Line and Monaural Microphone Inputs Bypass and Sidetone Paths to Output Line and Headphone Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Normal Mode USB Mode Software Control Interface Codec Pin Descriptions Register Details Bit Descriptions Specifications Operating Conditions Codec Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Power Consumption Timing Specifications TWI Timing SPI Timing Digital Audio Interface Slave Mode Timing Digital Audio Interface Master Mode Timing System Clock Timing Digital Filter Characteristics Converter Filter Response Digital De-Emphasis 289-Ball CSP_BGA Ball Assignment Outline Dimensions Ordering Guide
1/fS LEFT CHANNEL RIGHT CHANNEL ADCLRC/ DACLRC CODEC_BCLK ADCDAT/ X 1 2 3 4 N X X 1 2 3 N X DACDAT X = DON’T CARE.
Figure 8. I2S Audio Input Mode
1/fS LEFT CHANNEL RIGHT CHANNEL ADCLRC/ DACLRC CODEC_BCLK ADCDAT/ 1 2 3 N 1 2 3 N X X X DACDAT X = DON’T CARE.
Figure 9. Frame Sync/PCM Mode Audio Input (Submode 1) [Bit LRP = 0]
1/fS LEFT CHANNEL RIGHT CHANNEL ADCLRC/ DACLRC CODEC_BCLK ADCDAT/ X 1 2 3 N 1 2 3 N X X DACDAT X = DON’T CARE.
Figure 10. Frame Sync/PCM Mode Audio Input (Submode 2) [Bit LRP = 1] Rev. A | Page 7 of 36 | March 2010 Document Outline Blackfin Embedded Processor with Codec Processor Features Embedded Codec Features Peripherals Table of Contents Revision History General Description Codec Description ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Analog Audio Interfaces Stereo Line and Monaural Microphone Inputs Bypass and Sidetone Paths to Output Line and Headphone Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Normal Mode USB Mode Software Control Interface Codec Pin Descriptions Register Details Bit Descriptions Specifications Operating Conditions Codec Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Power Consumption Timing Specifications TWI Timing SPI Timing Digital Audio Interface Slave Mode Timing Digital Audio Interface Master Mode Timing System Clock Timing Digital Filter Characteristics Converter Filter Response Digital De-Emphasis 289-Ball CSP_BGA Ball Assignment Outline Dimensions Ordering Guide
