Datasheet ADSP-BF534, ADSP-BF536, ADSP-BF537 (Analog Devices) - 24

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ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 10 through Table 12 describe the voltage/frequency ratios so as not to exceed the maximum core clock and system requirements for the ADSP-BF534/ADSP-BF536/ADSP-BF537 clock. Table 13 describes phase-locked loop operating processor clocks. Take care in selecting MSEL, SSEL, and CSEL conditions.
Table 10. Core Clock Requirements—500 MHz, 533 MHz, and 600 MHz Speed Grades1 Parameter Internal Regulator Setting Max Unit
fCCLK Core Clock Frequency (VDDINT =1.30 V Minimum)2 1.30 V 600 MHz fCCLK Core Clock Frequency (VDDINT = 1.20 V Minimum)3 1.25 V 533 MHz fCCLK Core Clock Frequency (VDDINT =1.14 V Minimum) 1.20 V 500 MHz fCCLK Core Clock Frequency (VDDINT =1.045 V Minimum) 1.10 V 444 MHz fCCLK Core Clock Frequency (VDDINT = 0.95 V Minimum) 1.00 V 400 MHz fCCLK Core Clock Frequency (VDDINT = 0.85 V Minimum) 0.90 V 333 MHz fCCLK Core Clock Frequency (VDDINT = 0.8 V Minimum) 0.85 V 250 MHz 1 See Ordering Guide on Page 67. 2 Applies to 600 MHz models only. See Ordering Guide on Page 67. 3 Applies to 533 MHz and 600 MHz models only. See Ordering Guide on Page 67.
Table 11. Core Clock Requirements—400 MHz Speed Grade1 120°C

TJ

105°C All2 Other TJ Parameter Internal Regulator Setting Max Max Unit
fCCLK Core Clock Frequency (VDDINT =1.14 V Minimum) 1.20 V 400 400 MHz fCCLK Core Clock Frequency (VDDINT =1.045 V Minimum) 1.10 V 333 363 MHz fCCLK Core Clock Frequency (VDDINT = 0.95 V Minimum) 1.00 V 295 333 MHz fCCLK Core Clock Frequency (VDDINT = 0.85 V Minimum) 0.90 V 280 MHz fCCLK Core Clock Frequency (VDDINT = 0.8 V Minimum) 0.85 V 250 MHz 1 See Ordering Guide on Page 67. 2 See Operating Conditions on Page 23.
Table 12. Core Clock Requirements—300 MHz Speed Grade1 Parameter Internal Regulator Setting Max Unit
fCCLK Core Clock Frequency (VDDINT =1.14 V Minimum) 1.20 V 300 MHz fCCLK Core Clock Frequency (VDDINT =1.045 V Minimum) 1.10 V 255 MHz fCCLK Core Clock Frequency (VDDINT = 0.95 V Minimum) 1.00 V 210 MHz fCCLK Core Clock Frequency (VDDINT = 0.85 V Minimum) 0.90 V 180 MHz fCCLK Core Clock Frequency (VDDINT = 0.8 V Minimum) 0.85 V 160 MHz 1 See Ordering Guide on Page 67.
Table 13. Phase-Locked Loop Operating Conditions Parameter Min Max Unit
fVCO Voltage Controlled Oscillator (VCO) Frequency 50 Max fCCLK MHz
Table 14. System Clock Requirements Parameter Condition Max Unit
f 1  SCLK VDDEXT 3.3 V or 2.5 V, VDDINT  1.14 V 1332 MHz f 1  SCLK VDDEXT 3.3 V or 2.5 V, VDDINT  1.14 V 100 MHz 1 fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 27 on Page 34. 2 Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 27 on Page 34. Rev. J | Page 24 of 68 | February 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Ports Controller Area Network (CAN) TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing External Port Bus Request and Grant Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Port—Master Timing Serial Peripheral Interface Port—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing 10/100 Ethernet MAC Controller Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 182-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide