Datasheet ADSP-BF534, ADSP-BF536, ADSP-BF537 (Analog Devices) - 5

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ADSP-BF534/ADSP-BF536/ADSP-BF537
The address arithmetic unit provides two addresses for simulta- The memory DMA controller provides high bandwidth data- neous dual fetches from memory. It contains a multiported movement capability. It can perform block transfers of code or register file consisting of four sets of 32-bit index, modify, data between the internal memory and the external length, and base registers (for circular buffering), and eight memory spaces. additional 32-bit pointer registers (for C-style indexed stack manipulation).
Internal (On-Chip) Memory
Blackfin processors support a modified Harvard architecture in The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors have combination with a hierarchical memory structure. Level 1 (L1) three blocks of on-chip memory providing high-bandwidth memories are those that typically operate at the full processor access to the core. speed with little or no latency. At the L1 level, the instruction The first block is the L1 instruction memory, consisting of memory holds instructions only. The two data memories hold 64K bytes SRAM, of which 16K bytes can be configured as a data, and a dedicated scratchpad data memory stores stack and four-way set-associative cache. This memory is accessed at full local variable information. processor speed. In addition, multiple L1 memory blocks are provided, offering a The second on-chip memory block is the L1 data memory, con- configurable mix of SRAM and cache. The memory manage- sisting of up to two banks of up to 32K bytes each. Each memory ment unit (MMU) provides memory protection for individual bank is configurable, offering both cache and SRAM functional- tasks that may be operating on the core and can protect system ity. This memory block is accessed at full processor speed. registers from unintended access. The third memory block is a 4K byte scratchpad SRAM, which The architecture provides three modes of operation: user mode, runs at the same speed as the L1 memories, but is only accessible supervisor mode, and emulation mode. User mode has as data SRAM, and cannot be configured as cache memory. restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has
External (Off-Chip) Memory
unrestricted access to the system and core resources. External memory is accessed via the EBIU. This 16-bit interface The Blackfin processor instruction set has been optimized so provides a glueless connection to a bank of synchronous DRAM that 16-bit opcodes represent the most frequently used instruc- (SDRAM) as well as up to four banks of asynchronous memory tions, resulting in excellent compiled code density. Complex devices including flash, EPROM, ROM, SRAM, and memory DSP instructions are encoded into 32-bit opcodes, representing mapped I/O devices. fully featured multifunction instructions. Blackfin processors The PC133-compliant SDRAM controller can be programmed support a limited multi-issue capability, where a 32-bit instruc- to interface to up to 128M bytes of SDRAM. A separate row can tion can be issued in parallel with two 16-bit instructions, be open for each SDRAM internal bank, and the SDRAM con- allowing the programmer to use many of the core resources in a troller supports up to 4 internal SDRAM banks, improving single instruction cycle. overall performance. The Blackfin processor assembly language uses an algebraic syn- The asynchronous memory controller can be programmed to tax for ease of coding and readability. The architecture has been control up to four banks of devices with very flexible timing optimized for use in conjunction with the C/C++ compiler, parameters for a wide variety of devices. Each bank occupies a resulting in fast and efficient software implementations. 1M byte segment regardless of the size of the devices used, so that these banks are only contiguous if each is fully populated
MEMORY ARCHITECTURE
with 1M byte of memory. The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors view memory as a single unified 4G byte address space, using 32-bit
I/O Memory Space
addresses. All resources, including internal memory, external The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors do memory, and I/O control registers, occupy separate sections of not define a separate I/O space. All resources are mapped this common address space. The memory portions of this through the flat 32-bit address space. On-chip I/O devices have address space are arranged in a hierarchical structure to provide their control registers mapped into memory-mapped registers a good cost/performance balance of some very fast, low latency (MMRs) at addresses near the top of the 4G byte address space. on-chip memory as cache or SRAM, and larger, lower cost, and These are separated into two smaller blocks, one which contains performance off-chip memory systems. (See Figure 3). the control MMRs for all core functions, and the other which The on-chip L1 memory system is the highest performance contains the registers needed for setup and control of the on- memory available to the Blackfin processor. The off-chip mem- chip peripherals outside of the core. The MMRs are accessible ory system, accessed through the external bus interface unit only in supervisor mode and appear as reserved space to on- (EBIU), provides expansion with SDRAM, flash memory, and chip peripherals. SRAM, optionally accessing up to 516M bytes of
Booting
physical memory. The Blackfin processor contains a small on-chip boot kernel, which configures the appropriate peripheral for booting. If the Blackfin processor is configured to boot from boot ROM Rev. J | Page 5 of 68 | February 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Ports Controller Area Network (CAN) TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing External Port Bus Request and Grant Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Port—Master Timing Serial Peripheral Interface Port—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing 10/100 Ethernet MAC Controller Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 182-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide