Datasheet ADSP-BF534, ADSP-BF536, ADSP-BF537 (Analog Devices) - 7

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ADSP-BF534/ADSP-BF536/ADSP-BF537 Core Event Controller (CEC) Table 3. System Interrupt Controller (SIC)
The CEC supports nine general-purpose interrupts (IVG15–7),
Default Peripheral
in addition to the dedicated interrupt and exception events. Of
Peripheral Interrupt Event Mapping Interrupt ID
these general-purpose interrupts, the two lowest priority PLL Wakeup IVG7 0 interrupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt DMA Error (Generic) IVG7 1 inputs to support the peripherals of the Blackfin processor. DMAR0 Block Interrupt IVG7 1 Table 2 describes the inputs to the CEC, identifies their names DMAR1 Block Interrupt IVG7 1 in the event vector table (EVT), and lists their priorities. DMAR0 Overflow Error IVG7 1 DMAR1 Overflow Error IVG7 1
Table 2. Core Event Controller (CEC)
CAN Error IVG7 2
Priority
Ethernet Error (ADSP-BF536 and IVG7 2
(0 Is Highest) Event Class EVT Entry
ADSP-BF537 only) 0 E mulation/Test Control EMU SPORT 0 Error IVG7 2 1 Reset RST SPORT 1 Error IVG7 2 2 Nonmaskable Interrupt NMI PPI Error IVG7 2 3 Exception EVX SPI Error IVG7 2 4 Reserved — UART0 Error IVG7 2 5 Hardware Error IVHW UART1 Error IVG7 2 6 Core Timer IVTMR Real-Time Clock IVG8 3 7 General-Purpose Interrupt 7 IVG7 DMA Channel 0 (PPI) IVG8 4 8 General-Purpose Interrupt 8 IVG8 DMA Channel 3 (SPORT 0 Rx) IVG9 5 9 General-Purpose Interrupt 9 IVG9 DMA Channel 4 (SPORT 0 Tx) IVG9 6 10 General-Purpose Interrupt 10 IVG10 DMA Channel 5 (SPORT 1 Rx) IVG9 7 11 General-Purpose Interrupt 11 IVG11 DMA Channel 6 (SPORT 1 Tx) IVG9 8 12 General-Purpose Interrupt 12 IVG12 TWI IVG10 9 13 General-Purpose Interrupt 13 IVG13 DMA Channel 7 (SPI) IVG10 10 14 General-Purpose Interrupt 14 IVG14 DMA Channel 8 (UART0 Rx) IVG10 11 15 General-Purpose Interrupt 15 IVG15 DMA Channel 9 (UART0 Tx) IVG10 12 DMA Channel 10 (UART1 Rx) IVG10 13
System Interrupt Controller (SIC)
DMA Channel 11 (UART1 Tx) IVG10 14 The system interrupt controller provides the mapping and rout- CAN Rx IVG11 15 ing of events from the many peripheral interrupt sources to the CAN Tx IVG11 16 prioritized general-purpose interrupt inputs of the CEC. Although the processor provides a default mapping, the user DMA Channel 1 (Ethernet Rx, IVG11 17 can alter the mappings and priorities of interrupt events by writ- ADSP-BF536 and ADSP-BF537 only) ing the appropriate values into the interrupt assignment Port H Interrupt A IVG11 17 registers (IAR). Table 3 describes the inputs into the SIC and the DMA Channel 2 (Ethernet Tx, IVG11 18 default mappings into the CEC. ADSP-BF536 and ADSP-BF537 only) Port H Interrupt B IVG11 18 Timer 0 IVG12 19 Timer 1 IVG12 20 Timer 2 IVG12 21 Timer 3 IVG12 22 Timer 4 IVG12 23 Timer 5 IVG12 24 Timer 6 IVG12 25 Timer 7 IVG12 26 Port F, G Interrupt A IVG12 27 Port G Interrupt B IVG12 28 Rev. J | Page 7 of 68 | February 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Ports Controller Area Network (CAN) TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing External Port Bus Request and Grant Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Port—Master Timing Serial Peripheral Interface Port—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing 10/100 Ethernet MAC Controller Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 182-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide