Datasheet ADSP-BF531, ADSP-BF532, ADSP-BF533 (Analog Devices) - 8

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ADSP-BF531/ ADSP-BF532 /ADSP-BF533
• CEC interrupt pending register (IPEND) – The IPEND peripherals include the SPORTs, SPI port, UART, and PPI. Each register keeps track of all nested events. A set bit in the individual DMA-capable peripheral has at least one dedicated IPEND register indicates the event is currently active or DMA channel. nested at some level. This register is updated automatically The DMA controller supports both 1-dimensional (1-D) and 2- by the controller but can be read while in supervisor mode. dimensional (2-D) DMA transfers. DMA transfer initialization The SIC allows further control of event processing by providing can be implemented from registers or from sets of parameters three 32-bit interrupt control and status registers. Each register called descriptor blocks. contains a bit corresponding to each of the peripheral interrupt The 2-D DMA capability supports arbitrary row and column events shown in Table 3. sizes up to 64K elements by 64K elements, and arbitrary row • SIC interrupt mask register (SIC_IMASK) – This register and column step sizes up to ±32K elements. Furthermore, the controls the masking and unmasking of each peripheral column step size can be less than the row step size, allowing interrupt event. When a bit is set in this register, that implementation of interleaved data streams. This feature is peripheral event is unmasked and is processed by the sys- especially useful in video applications where data can be tem when asserted. A cleared bit in this register masks the de-interleaved on the fly. peripheral event, preventing the processor from servicing Examples of DMA types supported by the DMA controller the event. include: • SIC interrupt status register (SIC_ISR) – As multiple • A single, linear buffer that stops upon completion peripherals can be mapped to a single event, this register allows the software to determine which peripheral event • A circular, autorefreshing buffer that interrupts on each source triggered the interrupt. A set bit indicates the full or fractionally full buffer peripheral is asserting the interrupt, and a cleared bit indi- • 1-D or 2-D DMA using a linked list of descriptors cates the peripheral is not asserting the event. • 2-D DMA using an array of descriptors, specifying only the • SIC interrupt wakeup enable register (SIC_IWR) – By base DMA address within a common page enabling the corresponding bit in this register, a peripheral In addition to the dedicated peripheral DMA channels, there are can be configured to wake up the processor, should the two pairs of memory DMA channels provided for transfers core be idled when the event is generated. See Dynamic between the various memories of the processor system. This Power Management on Page 11. enables transfers of blocks of data between any of the memo- Because multiple interrupt sources can map to a single general- ries—including external SDRAM, ROM, SRAM, and flash purpose interrupt, multiple pulse assertions can occur simulta- memory—with minimal processor intervention. Memory DMA neously, before or during interrupt processing for an interrupt transfers can be controlled by a very flexible descriptor-based event already detected on this interrupt input. The IPEND reg- methodology or by a standard register-based autobuffer ister contents are monitored by the SIC as the interrupt mechanism. acknowledgement.
REAL-TIME CLOCK
The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The The processor real-time clock (RTC) provides a robust set of bit is cleared when the respective IPEND register bit is set. The digital watch features, including current time, stopwatch, and IPEND bit indicates that the event has entered into the proces- alarm. The RTC is clocked by a 32.768 kHz crystal external to sor pipeline. At this point the CEC recognizes and queues the the ADSP-BF531/ADSP-BF532/ADSP-BF533 processors. The next rising edge event on the corresponding event input. The RTC peripheral has dedicated power supply pins so that it can minimum latency from the rising edge transition of the remain powered up and clocked even when the rest of the pro- general-purpose interrupt to the IPEND output asserted is three cessor is in a low power state. The RTC provides several core clock cycles; however, the latency can be much higher, programmable interrupt options, including interrupt per sec- depending on the activity within and the state of the processor. ond, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a pro-
DMA CONTROLLERS
grammed alarm time. The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have The 32.768 kHz input clock frequency is divided down to a 1 Hz multiple, independent DMA channels that support automated signal by a prescaler. The counter function of the timer consists data transfers with minimal overhead for the processor core. of four counters: a 60 second counter, a 60 minute counter, a DMA transfers can occur between the processor’s internal 24 hour counter, and a 32,768 day counter. memories and any of its DMA-capable peripherals. Addition- When enabled, the alarm function generates an interrupt when ally, DMA transfers can be accomplished between any of the the output of the timer matches the programmed value in the DMA-capable peripherals and external devices connected to the alarm control register. The two alarms are time of day and a day external memory interfaces, including the SDRAM controller and time of that day. and the asynchronous memory controller. DMA-capable Rev. I | Page 8 of 64 | August 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port General-Purpose I/O Port F Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing General-Purpose I/O Port F Pin Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 160-Ball CSP_BGA Ball Assignment 169-Ball PBGA Ball Assignment 176-Lead LQFP Pinout Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide