Datasheet ADSP-BF531, ADSP-BF532, ADSP-BF533 (Analog Devices) - 10

ADSP-BF531/ ADSP-BF532 /ADSP-BF533
• Interrupts – Each transmit and receive port generates an • DMA (direct memory access) – The DMA controller trans- interrupt upon completing the transfer of a data-word or fers both transmit and receive data. This reduces the after transferring an entire data buffer or buffers number and frequency of interrupts required to transfer through DMA. data to and from memory. The UART has two dedicated • Multichannel capability – Each SPORT supports 128 chan- DMA channels, one for transmit and one for receive. These nels out of a 1,024-channel window and is compatible with DMA channels have lower default priority than most DMA the H.100, H.110, MVIP-90, and HMVIP standards. channels because of their relatively low service rates. An additional 250 mV of SPORT input hysteresis can be The baud rate, serial data format, error code generation and sta- enabled by setting Bit 15 of the PLL_CTL register. When this bit tus, and interrupts for the UART port are programmable. is set, all SPORT input pins have the increased hysteresis. The UART programmable features include:
SERIAL PERIPHERAL INTERFACE (SPI) PORT
• Supporting bit rates ranging from (fSCLK/1,048,576) bits per second to (fSCLK/16) bits per second. The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have • Supporting data formats from seven bits to 12 bits per an SPI-compatible port that enables the processor to communi- frame. cate with multiple SPI-compatible devices. • Both transmit and receive operations can be configured to The SPI interface uses three pins for transferring data: two data generate maskable interrupts to the processor. pins (master output-slave input, MOSI, and master input-slave output, MISO) and a clock pin (serial clock, SCK). An SPI chip The UART port’s clock rate is calculated as: select input pin (SPISS) lets other SPI devices select the proces- fSCLK sor, and seven SPI chip select output pins (SPISEL7–1) let the UART Clock Rate = ------------------------ 16  UART_Divisor processor select other SPI devices. The SPI select pins are recon- figured general-purpose I/O pins. Using these pins, the SPI port where the 16-bit UART_Divisor comes from the UART_DLH provides a full-duplex, synchronous serial interface which sup- register (most significant 8 bits) and UART_DLL register (least ports both master/slave modes and multimaster environments. significant 8 bits). The baud rate and clock phase/polarities for the SPI port are In conjunction with the general-purpose timer functions, programmable, and it has an integrated DMA controller, con- autobaud detection is supported. figurable to support transmit or receive data streams. The SPI The capabilities of the UART are further extended with support DMA controller can only service unidirectional accesses at any for the Infrared Data Association (IrDA®) serial infrared physi- given time. cal layer link specification (SIR) protocol. The SPI port clock rate is calculated as:
GENERAL-PURPOSE I/O PORT F
fSCLK The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have SPI Clock Rate = ------------------ 2  SPI_BAUD 16 bidirectional, general-purpose I/O pins on Port F (PF15–0). Each general-purpose I/O pin can be individually controlled by where the 16-bit SPI_BAUD register contains a value of 2 to manipulation of the GPIO control, status and interrupt 65,535. registers: During transfers, the SPI port simultaneously transmits and • GPIO direction control register – Specifies the direction of receives by serially shifting data in and out on its two serial data each individual PFx pin as input or output. lines. The serial clock line synchronizes the shifting and sam- • GPIO contro l and status registers – The processor employs pling of data on the two serial data lines. a “write one to modify” mechanism that allows any combi-
UART PORT
nation of individual GPIO pins to be modified in a single instruction, without affecting the level of any other GPIO The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors pro- pins. Four control registers are provided. One register is vide a full-duplex universal asynchronous receiver/transmitter written in order to set GPIO pin values, one register is writ- (UART) port, which is fully compatible with PC-standard ten in order to clear GPIO pin values, one register is written UARTs. The UART port provides a simplified UART interface in order to toggle GPIO pin values, and one register is writ- to other peripherals or hosts, supporting full-duplex, DMA-sup- ten in order to specify GPIO pin values. Reading the GPIO ported, asynchronous transfers of serial data. The UART port status register allows software to interrogate the sense of includes support for 5 data bits to 8 data bits, 1 stop bit or 2 stop the GPIO pin. bits, and none, even, or odd parity. The UART port supports two modes of operation: • GPIO interrupt mask registers – The two GPIO interrupt mask registers allow each individual PFx pin to function as • PIO (programmed I/O) – The processor sends or receives an interrupt to the processor. Similar to the two GPIO data by writing or reading I/O-mapped UART registers. control registers that are used to set and clear individual The data is double-buffered on both transmit and receive. GPIO pin values, one GPIO interrupt mask register sets bits to enable interrupt function, and the other GPIO inter- rupt mask register clears bits to disable interrupt function. Rev. I | Page 10 of 64 | August 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port General-Purpose I/O Port F Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing General-Purpose I/O Port F Pin Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 160-Ball CSP_BGA Ball Assignment 169-Ball PBGA Ball Assignment 176-Lead LQFP Pinout Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide