Datasheet ADSP-BF531, ADSP-BF532, ADSP-BF533 (Analog Devices) - 3

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ADSP-BF531/ ADSP-BF532 /ADSP-BF533 GENERAL DESCRIPTION
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are
PORTABLE LOW POWER ARCHITECTURE
members of the Blackfin® family of products, incorporating the Blackfin processors provide world-class power management Analog Devices, Inc./Intel Micro Signal Architecture (MSA). and performance. Blackfin processors are designed in a low Blackfin processors combine a dual-MAC state-of-the-art signal power and low voltage design methodology and feature processing engine, the advantages of a clean, orthogonal RISC- dynamic power management—the ability to vary both the volt- like microprocessor instruction set, and single instruction, mul- age and frequency of operation to significantly lower overall tiple data (SIMD) multimedia capabilities into a single power consumption. Varying the voltage and frequency can instruction set architecture. result in a substantial reduction in power consumption, com- The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are pared with just varying the frequency of operation. This completely code and pin-compatible, differing only with respect translates into longer battery life for portable appliances. to their performance and on-chip memory. Specific perfor- mance and memory configurations are shown in Table 1.
SYSTEM INTEGRATION
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are
Table 1. Processor Comparison
highly integrated system-on-a-chip solutions for the next gener- ation of digital communication and consumer multimedia applications. By combining industry-standard interfaces with a
-BF531 -BF532 -BF533
high performance signal processing core, users can develop cost-effective solutions quickly without the need for costly
Features ADSP ADSP ADSP
external components. The system peripherals include a UART port, an SPI port, two serial ports (SPORTs), four general-pur- SPORTs 2 2 2 pose timers (three with PWM capability), a real-time clock, a UART 1 1 1 watchdog timer, and a parallel peripheral interface. SPI 1 1 1 GP Timers 3 3 3
PROCESSOR PERIPHERALS
Watchdog Timers 1 1 1 The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors con- RTC 1 1 1 tain a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configura- Parallel Peripheral Interface 1 1 1 tion as well as excellent overall system performance (see the GPIOs 16 16 16 functional block diagram in Figure 1 on Page 1). The general- L1 Instruction SRAM/Cache 16K bytes 16K bytes 16K bytes purpose peripherals include functions such as UART, timers ation L1 Instruction SRAM 16K bytes 32K bytes 64K bytes with PWM (pulse-width modulation) and pulse measurement L1 Data SRAM/Cache 16K bytes 32K bytes 32K bytes capability, general-purpose I/O pins, a real-time clock, and a nfigur o watchdog timer. This set of functions satisfies a wide variety of L1 Data SRAM 32K bytes C y typical system support needs and is augmented by the system L1 Scratchpad 4K bytes 4K bytes 4K bytes expansion capabilities of the part. In addition to these general- L3 Boot ROM 1K bytes 1K bytes 1K bytes purpose peripherals, the processors contain high speed serial Memor and parallel ports for interfacing to a variety of audio, video, and Maximum Speed Grade 400 MHz 400 MHz 600 MHz modem codec functions; an interrupt controller for flexible Package Options: management of interrupts from the on-chip peripherals or CSP_BGA 160-Ball 160-Ball 160-Ball external sources; and power management control functions to Plastic BGA 169-Ball 169-Ball 169-Ball tailor the performance and power characteristics of the proces- 176-Lead 176-Lead 176-Lead sor and system to many application scenarios. LQFP All of the peripherals, except for general-purpose I/O, real-time By integrating a rich set of industry-leading system peripherals clock, and timers, are supported by a flexible DMA structure. and memory, Blackfin processors are the platform of choice for There is also a separate memory DMA channel dedicated to next generation applications that require RISC-like program- data transfers between the processor’s various memory spaces, mability, multimedia support, and leading-edge signal including external SDRAM and asynchronous memory. Multi- processing in one integrated package. ple on-chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activ- ity on all of the on-chip and external peripherals. The processors include an on-chip voltage regulator in support of the processor’s dynamic power management capability. The voltage regulator provides a range of core voltage levels from VDDEXT. The voltage regulator can be bypassed at the user’s discretion. Rev. I | Page 3 of 64 | August 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port General-Purpose I/O Port F Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing General-Purpose I/O Port F Pin Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 160-Ball CSP_BGA Ball Assignment 169-Ball PBGA Ball Assignment 176-Lead LQFP Pinout Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide