Datasheet ADSP-BF531, ADSP-BF532, ADSP-BF533 (Analog Devices)

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Blackfin Embedded Processor ADSP-BF531/ ADSP-BF532 /ADSP-BF533 FEATURES PERIPHERALS Up to 600 MHz high performance Blackfin processor Parallel peripheral interface PPI, supporting Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, ITU-R 656 video data formats 40-bit shifter 2 dual-channel, full duplex synchronous serial ports, sup- RISC-like register and instruction model for ease of pro- porting eight stereo I2S channels gramming and compiler-friendly support 2 memory-to-memory DMAs Advanced debug, trace, and performance monitoring 8 peripheral DMAs Wide range of operating voltages (see Operating Conditions SPI-compatible port on Page 20) Three 32-bit timer/counters with PWM support Qualified for Automotive Applications (see Automotive Prod- Real-time clock and watchdog timer ucts on Page 62 ) 32-bit core timer Programmable on-chip voltage regulator Up to 16 general-purpose I/O pins (GPIO) 160-ball CSP_BGA, 169-ball PBGA, and 176-lead LQFP UART with support for IrDA packages Event handler MEMORY Debug/JTAG interface Up to 148K bytes of on-chip memory (see Table 1 on Page 3 ) On-chip PLL capable of frequency multiplication Memory management unit providing memory protection External memory controller with glueless support for SDRAM, SRAM, flash, and ROM Flexible memory booting options from SPI and external memory VOLTAGE REGULATOR JTAG TEST AND EMULATION US B SS INTERRUPT E WATCHDOG
B
CONTROLLER CC A TIMER AL R HE RTC IP ER L1 L1 P DMA PPI INSTRUCTION DATA CONTROLLER MEMORY MEMORY GPIO S TIMER0-2 PORT BU F DMA SS EXTERNAL CE SPI DMA CORE BUS BUS C EXTERNAL ACCESS BUS A MA D UART EXTERNAL PORT FLASH, SDRAM CONTROL SPORT0-1 16 BOOT ROM
Figure 1. Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
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Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port General-Purpose I/O Port F Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing General-Purpose I/O Port F Pin Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 160-Ball CSP_BGA Ball Assignment 169-Ball PBGA Ball Assignment 176-Lead LQFP Pinout Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide