Datasheet ADSP-BF531, ADSP-BF532, ADSP-BF533 (Analog Devices) - 4

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ADSP-BF531/ ADSP-BF532 /ADSP-BF533 BLACKFIN PROCESSOR CORE
In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The memory manage- As shown in Figure 2 on Page 5, the Blackfin processor core ment unit (MMU) provides memory protection for individual contains two 16-bit multipliers, two 40-bit accumulators, two tasks that may be operating on the core and can protect system 40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu- registers from unintended access. tation units process 8-bit, 16-bit, or 32-bit data from the register file. The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has The compute register file contains eight 32-bit registers. When restricted access to certain system resources, thus providing a performing compute operations on 16-bit operand data, the protected software environment, while supervisor mode has register file operates as 16 independent 16-bit registers. All unrestricted access to the system and core resources. operands for compute operations come from the multiported register file and instruction constant fields. The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instruc- Each MAC can perform a 16-bit by 16-bit multiply in each tions, resulting in excellent compiled code density. Complex cycle, accumulating the results into the 40-bit accumulators. DSP instructions are encoded into 32-bit opcodes, representing Signed and unsigned formats, rounding, and saturation are fully featured multifunction instructions. Blackfin processors supported. support a limited multi-issue capability, where a 32-bit instruc- The ALUs perform a traditional set of arithmetic and logical tion can be issued in parallel with two 16-bit instructions, operations on 16-bit or 32-bit data. In addition, many special allowing the programmer to use many of the core resources in a instructions are included to accelerate various signal processing single instruction cycle. tasks. These include bit operations such as field extract and The Blackfin processor assembly language uses an algebraic syn- population count, modulo 232 multiply, divide primitives, satu- tax for ease of coding and readability. The architecture has been ration and rounding, and sign/exponent detection. The set of optimized for use in conjunction with the C/C++ compiler, video instructions includes byte alignment and packing opera- resulting in fast and efficient software implementations. tions, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA)
MEMORY ARCHITECTURE
operations. Also provided are the compare/select and vector search instructions. The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors view memory as a single unified 4G byte address space, using 32-bit For certain instructions, two 16-bit ALU operations can be per- addresses. All resources, including internal memory, external formed simultaneously on register pairs (a 16-bit high half and memory, and I/O control registers, occupy separate sections of 16-bit low half of a compute register). Quad 16-bit operations this common address space. The memory portions of this are possible using the second ALU. address space are arranged in a hierarchical structure to provide The 40-bit shifter can perform shifts and rotates and is used to a good cost/performance balance of some very fast, low latency support normalization, field extract, and field deposit on-chip memory as cache or SRAM, and larger, lower cost and instructions. performance off-chip memory systems. See Figure 3, Figure 4, and Figure 5 on Page 6. The program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. For The L1 memory system is the primary highest performance program flow control, the sequencer supports PC relative and memory available to the Blackfin processor. The off-chip mem- indirect conditional jumps (with static branch prediction), and ory system, accessed through the external bus interface unit subroutine calls. Hardware is provided to support zero-over- (EBIU), provides expansion with SDRAM, flash memory, and head looping. The architecture is fully interlocked, meaning that SRAM, optionally accessing up to 132M bytes of the programmer need not manage the pipeline when executing physical memory. instructions with data dependencies. The memory DMA controller provides high bandwidth data- The address arithmetic unit provides two addresses for simulta- movement capability. It can perform block transfers of code or neous dual fetches from memory. It contains a multiported data between the internal memory and the external register file consisting of four sets of 32-bit index, modify, memory spaces. length, and base registers (for circular buffering), and eight
Internal (On-Chip) Memory
additional 32-bit pointer registers (for C-style indexed stack manipulation). The processors have three blocks of on-chip memory that pro- Blackfin processors support a modified Harvard architecture in vide high bandwidth access to the core. combination with a hierarchical memory structure. Level 1 (L1) The first block is the L1 instruction memory, consisting of up to memories are those that typically operate at the full processor 80K bytes SRAM, of which 16K bytes can be configured as a speed with little or no latency. At the L1 level, the instruction four way set-associative cache. This memory is accessed at full memory holds instructions only. The two data memories hold processor speed. data, and a dedicated scratchpad data memory stores stack and local variable information. Rev. I | Page 4 of 64 | August 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port General-Purpose I/O Port F Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing General-Purpose I/O Port F Pin Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 160-Ball CSP_BGA Ball Assignment 169-Ball PBGA Ball Assignment 176-Lead LQFP Pinout Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide