Datasheet ADAU1702 (Analog Devices) - 2
| Manufacturer | Analog Devices |
| Description | SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs |
| Pages / Page | 52 / 2 — ADAU1702. Data Sheet. TABLE OF CONTENTS |
| Revision | D |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
ADAU1702. Data Sheet. TABLE OF CONTENTS
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ADAU1702 Data Sheet TABLE OF CONTENTS
Features .. 1 Parameter RAM .. 30 Applications ... 1 Data RAM ... 30 General Description ... 1 Read/Write Data Formats ... 30 Revision History ... 3 Control Register Map ... 32 Functional Block Diagram .. 4 Control Register Details .. 34 Specifications ... 5 Address 2048 to Address 2055 (0x0800 to 0x0807)—Interface Analog Performance .. 5 Registers ... 34 Digital Input/Output .. 6 Address 2056 (0x0808)—GPIO Pin Setting Register .. 35 Power .. 6 Address 2057 to Address 2060 (0x0809 to 0x080C)— Auxiliary ADC Data Registers.. 36 PLL and Oscil ator .. 6 Address 2064 to Address 2068 (0x0810 to 0x0814)—Safeload Regulator.. 6 Data Registers ... 37 Digital Timing Specifications ... 7 Address 2069 to Address 2073 (0x0815 to 0x0819)—Safeload Absolute Maximum Ratings .. 10 Address Registers ... 37 Thermal Resistance .. 10 Address 2074 to Address 2075 (0x081A to 0x081B)—Data ESD Caution .. 10 Capture Registers.. 38 Pin Configuration and Function Descriptions ... 11 Address 2076 (0x081C)—DSP Core Control Register .. 39 Typical Performance Characteristics ... 14 Address 2078 (0x081E)—Serial Output Control Register .. 40 System Block Diagram ... 15 Address 2079 (0x081F)—Serial Input Control Register ... 41 Theory of Operation .. 16 Address 2080 to Address 2081 (0x0820 to 0x0821)— Multipurpose Pin Configuration Registers .. 42 Initialization .. 17 Address 2082 (0x0822)—Auxiliary ADC and Power Control Power-Up Sequence ... 17 Register .. 43 Control Registers Setup ... 17 Address 2084 (0x0824)—Auxiliary ADC Enable Register ... 43 Recommended Program/Parameter Loading Procedure ... 17 Address 2086 (0x0826)—Oscillator Power-Down Register . 43 Power Reduction Modes .. 18 Address 2087 (0x0827)—DAC Setup .. 44 Using the Oscillator .. 18 Multipurpose Pins .. 45 Setting Master Clock/PLL Mode .. 18 Auxiliary ADC .. 45 Voltage Regulator ... 19 General-Purpose Input/Output Pins ... 45 Audio ADCs .. 20 Serial Data Input/Output Ports .. 45 Audio DACs .. 21 Layout Recommendations ... 48 Control Ports ... 22 Parts Placement .. 48 I2C Port... 23 Grounding ... 48 SPI Port .. 26 Typical Application Schematics .. 49 Self-Boot .. 27 Self-Boot Mode ... 49 Signal Processing .. 29 I2C Control .. 50 Numeric Formats .. 29 SPI Control .. 51 Programming .. 29 Outline Dimensions ... 52 RAMs and Registers ... 30 Ordering Guide .. 52 Address Maps .. 30 Rev. D | Page 2 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE DIGITAL INPUT/OUTPUT POWER PLL AND OSCILLATOR REGULATOR DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION INITIALIZATION POWER-UP SEQUENCE CONTROL REGISTERS SETUP DSP Core Control Register (Address 2076) DAC Setup Register (Address 2087) RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURE POWER REDUCTION MODES USING THE OSCILLATOR SETTING MASTER CLOCK/PLL MODE VOLTAGE REGULATOR AUDIO ADCs AUDIO DACs CONTROL PORTS I2C PORT Addressing I2C Read and Write Operations SPI PORT Chip Address R/ Subaddress Data Bytes SELF-BOOT EEPROM Format Writeback SIGNAL PROCESSING NUMERIC FORMATS Numerical Format: 5.23 PROGRAMMING RAMS AND REGISTERS ADDRESS MAPS PARAMETER RAM Direct Read/Write Safeload Write DATA RAM READ/WRITE DATA FORMATS CONTROL REGISTER MAP CONTROL REGISTER DETAILS ADDRESS 2048 TO ADDRESS 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS ADDRESS 2056 (0x0808)—GPIO PIN SETTING REGISTER ADDRESS 2057 TO ADDRESS 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS ADDRESS 2064 TO ADDRESS 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS ADDRESS 2069 TO ADDRESS 2073 (0x0815 TO 0x0819)—SAFELOAD ADDRESS REGISTERS ADDRESS 2074 TO ADDRESS 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS ADDRESS 2076 (0x081C)—DSP CORE CONTROL REGISTER ADDRESS 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER ADDRESS 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER ADDRESS 2080 TO ADDRESS 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS ADDRESS 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL REGISTER ADDRESS 2084 (0x0824)—AUXILIARY ADC ENABLE REGISTER ADDRESS 2086 (0x0826)—OSCILLATOR POWER-DOWN REGISTER ADDRESS 2087 (0x0827)—DAC SETUP MULTIPURPOSE PINS AUXILIARY ADC GENERAL-PURPOSE INPUT/OUTPUT PINS SERIAL DATA INPUT/OUTPUT PORTS LAYOUT RECOMMENDATIONS PARTS PLACEMENT GROUNDING TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE I2C CONTROL SPI CONTROL OUTLINE DIMENSIONS ORDERING GUIDE
ADAU1702 Data Sheet TABLE OF CONTENTS
Features .. 1 Parameter RAM .. 30 Applications ... 1 Data RAM ... 30 General Description ... 1 Read/Write Data Formats ... 30 Revision History ... 3 Control Register Map ... 32 Functional Block Diagram .. 4 Control Register Details .. 34 Specifications ... 5 Address 2048 to Address 2055 (0x0800 to 0x0807)—Interface Analog Performance .. 5 Registers ... 34 Digital Input/Output .. 6 Address 2056 (0x0808)—GPIO Pin Setting Register .. 35 Power .. 6 Address 2057 to Address 2060 (0x0809 to 0x080C)— Auxiliary ADC Data Registers.. 36 PLL and Oscil ator .. 6 Address 2064 to Address 2068 (0x0810 to 0x0814)—Safeload Regulator.. 6 Data Registers ... 37 Digital Timing Specifications ... 7 Address 2069 to Address 2073 (0x0815 to 0x0819)—Safeload Absolute Maximum Ratings .. 10 Address Registers ... 37 Thermal Resistance .. 10 Address 2074 to Address 2075 (0x081A to 0x081B)—Data ESD Caution .. 10 Capture Registers.. 38 Pin Configuration and Function Descriptions ... 11 Address 2076 (0x081C)—DSP Core Control Register .. 39 Typical Performance Characteristics ... 14 Address 2078 (0x081E)—Serial Output Control Register .. 40 System Block Diagram ... 15 Address 2079 (0x081F)—Serial Input Control Register ... 41 Theory of Operation .. 16 Address 2080 to Address 2081 (0x0820 to 0x0821)— Multipurpose Pin Configuration Registers .. 42 Initialization .. 17 Address 2082 (0x0822)—Auxiliary ADC and Power Control Power-Up Sequence ... 17 Register .. 43 Control Registers Setup ... 17 Address 2084 (0x0824)—Auxiliary ADC Enable Register ... 43 Recommended Program/Parameter Loading Procedure ... 17 Address 2086 (0x0826)—Oscillator Power-Down Register . 43 Power Reduction Modes .. 18 Address 2087 (0x0827)—DAC Setup .. 44 Using the Oscillator .. 18 Multipurpose Pins .. 45 Setting Master Clock/PLL Mode .. 18 Auxiliary ADC .. 45 Voltage Regulator ... 19 General-Purpose Input/Output Pins ... 45 Audio ADCs .. 20 Serial Data Input/Output Ports .. 45 Audio DACs .. 21 Layout Recommendations ... 48 Control Ports ... 22 Parts Placement .. 48 I2C Port... 23 Grounding ... 48 SPI Port .. 26 Typical Application Schematics .. 49 Self-Boot .. 27 Self-Boot Mode ... 49 Signal Processing .. 29 I2C Control .. 50 Numeric Formats .. 29 SPI Control .. 51 Programming .. 29 Outline Dimensions ... 52 RAMs and Registers ... 30 Ordering Guide .. 52 Address Maps .. 30 Rev. D | Page 2 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE DIGITAL INPUT/OUTPUT POWER PLL AND OSCILLATOR REGULATOR DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION INITIALIZATION POWER-UP SEQUENCE CONTROL REGISTERS SETUP DSP Core Control Register (Address 2076) DAC Setup Register (Address 2087) RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURE POWER REDUCTION MODES USING THE OSCILLATOR SETTING MASTER CLOCK/PLL MODE VOLTAGE REGULATOR AUDIO ADCs AUDIO DACs CONTROL PORTS I2C PORT Addressing I2C Read and Write Operations SPI PORT Chip Address R/ Subaddress Data Bytes SELF-BOOT EEPROM Format Writeback SIGNAL PROCESSING NUMERIC FORMATS Numerical Format: 5.23 PROGRAMMING RAMS AND REGISTERS ADDRESS MAPS PARAMETER RAM Direct Read/Write Safeload Write DATA RAM READ/WRITE DATA FORMATS CONTROL REGISTER MAP CONTROL REGISTER DETAILS ADDRESS 2048 TO ADDRESS 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS ADDRESS 2056 (0x0808)—GPIO PIN SETTING REGISTER ADDRESS 2057 TO ADDRESS 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS ADDRESS 2064 TO ADDRESS 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS ADDRESS 2069 TO ADDRESS 2073 (0x0815 TO 0x0819)—SAFELOAD ADDRESS REGISTERS ADDRESS 2074 TO ADDRESS 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS ADDRESS 2076 (0x081C)—DSP CORE CONTROL REGISTER ADDRESS 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER ADDRESS 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER ADDRESS 2080 TO ADDRESS 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS ADDRESS 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL REGISTER ADDRESS 2084 (0x0824)—AUXILIARY ADC ENABLE REGISTER ADDRESS 2086 (0x0826)—OSCILLATOR POWER-DOWN REGISTER ADDRESS 2087 (0x0827)—DAC SETUP MULTIPURPOSE PINS AUXILIARY ADC GENERAL-PURPOSE INPUT/OUTPUT PINS SERIAL DATA INPUT/OUTPUT PORTS LAYOUT RECOMMENDATIONS PARTS PLACEMENT GROUNDING TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE I2C CONTROL SPI CONTROL OUTLINE DIMENSIONS ORDERING GUIDE
