Datasheet ADAU1702 (Analog Devices) - 3

Data Sheet ADAU1702 REVISION HISTORY 5/16—Rev. C to Rev. D
Changes to Figure 5 .. 10 Changes to Audio DACs Section and Figure 19 ... 21 Changes to Table 8 .. 11 Changes to Table 10 .. 12
6/11—Rev. B to Rev. C
Changes to Figure 8 to Figure 11 .. 15 Deleted Table 2 .. 6 Renamed Theory of Operation Section .. 17 Changes to Initialization Section .. 18
2/11—Rev. A to Rev. B
Changes to Setting the Master Clock/PLL Mode Section ... 19 Changes to Test Conditions/Comments Column, Table 3 .. 8 Changes to Voltage Regulator Section ... 20 Changes to Table 10 .. 12 Changes to Figure 19 .. 22 Changes to Figure 20, Figure 21 .. 25 Changes to Table 14 .. 23 Changes to Figure 27 .. 27 Changes to Figure 22 through Figure 25.. 26 Deleted Table 20 .. 27
9/10—Rev. 0 to Rev. A
Changes to Self-Boot Section and EEPROM Format Section .. 28 Deleted Temperature Range Section and Table 4, Renumbered Added Figure 28, Renumbered Sequentially ... 29 Sequentially .. 4 Changes to Address 2057 to Address 2060 (0x809 to 0x80C)— Moved and Changes to Functional Block Diagram Section and Auxiliary ADC Data Registers Section .. 37 Figure 1 ... 4 Changes to Multipurpose Pins Section and Auxiliary ADC Changes to Table 1 .. 5 Section .. 46 Added Table 2; Renumbered Sequential y ... 6 Changes to Ordering Guide ... 56 Changes to Table 3 and Table 5 ... 7 Changes to Table 7 .. 8
7/07—Revision 0: Initial Version
Reorganized Digital Timing Diagrams Section .. 9 Changes to Figure 2... 9 Rev. D | Page 3 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE DIGITAL INPUT/OUTPUT POWER PLL AND OSCILLATOR REGULATOR DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION INITIALIZATION POWER-UP SEQUENCE CONTROL REGISTERS SETUP DSP Core Control Register (Address 2076) DAC Setup Register (Address 2087) RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURE POWER REDUCTION MODES USING THE OSCILLATOR SETTING MASTER CLOCK/PLL MODE VOLTAGE REGULATOR AUDIO ADCs AUDIO DACs CONTROL PORTS I2C PORT Addressing I2C Read and Write Operations SPI PORT Chip Address R/ Subaddress Data Bytes SELF-BOOT EEPROM Format Writeback SIGNAL PROCESSING NUMERIC FORMATS Numerical Format: 5.23 PROGRAMMING RAMS AND REGISTERS ADDRESS MAPS PARAMETER RAM Direct Read/Write Safeload Write DATA RAM READ/WRITE DATA FORMATS CONTROL REGISTER MAP CONTROL REGISTER DETAILS ADDRESS 2048 TO ADDRESS 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS ADDRESS 2056 (0x0808)—GPIO PIN SETTING REGISTER ADDRESS 2057 TO ADDRESS 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS ADDRESS 2064 TO ADDRESS 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS ADDRESS 2069 TO ADDRESS 2073 (0x0815 TO 0x0819)—SAFELOAD ADDRESS REGISTERS ADDRESS 2074 TO ADDRESS 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS ADDRESS 2076 (0x081C)—DSP CORE CONTROL REGISTER ADDRESS 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER ADDRESS 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER ADDRESS 2080 TO ADDRESS 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS ADDRESS 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL REGISTER ADDRESS 2084 (0x0824)—AUXILIARY ADC ENABLE REGISTER ADDRESS 2086 (0x0826)—OSCILLATOR POWER-DOWN REGISTER ADDRESS 2087 (0x0827)—DAC SETUP MULTIPURPOSE PINS AUXILIARY ADC GENERAL-PURPOSE INPUT/OUTPUT PINS SERIAL DATA INPUT/OUTPUT PORTS LAYOUT RECOMMENDATIONS PARTS PLACEMENT GROUNDING TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE I2C CONTROL SPI CONTROL OUTLINE DIMENSIONS ORDERING GUIDE