Datasheet ADuM4137 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | High Voltage, Isolated IGBT Gate Driver with Fault Detection |
| Pages / Page | 28 / 8 — ADuM4137. Data Sheet. SPI TIMING SPECIFICATIONS. Table 2. Parameter. … |
| File Format / Size | PDF / 673 Kb |
| Document Language | English |
ADuM4137. Data Sheet. SPI TIMING SPECIFICATIONS. Table 2. Parameter. Description. Min. Typ. Max. Unit. SPI Timing Diagram. HIGH. tCLK. LOW
Model Line for this Datasheet
Text Version of Document
ADuM4137 Data Sheet SPI TIMING SPECIFICATIONS
SPI timing specifications are guaranteed by design. Al devices are production tested with 200 kHz SPI communication.
Table 2. Parameter Description Min Typ Max Unit
tS Time to first clock edge 8 µs tDS Set period 1 µs tDH Hold period 1 µs tCLK Clock period 5 µs tH Release time 8 µs tHIGH Clock time high 100 ns tLOW Clock time low 100 ns tOV Output valid time 240 ns
SPI Timing Diagram t t DS HIGH tCLK t t t t S DH LOW H UVLO_FAULT CS SCLK DON’T CARE DON’T CARE MOSI DON’T CARE MBZ RW0 A1 A0 MBZ MBZ MBZ MBZ D23 D5 D4 D3 D1 D0 DON’T CARE tOV
002
MISO HIGH-Z 0 RW0′ A1′ A0′ 0 0 0 0 D23′ D5′ D4′ D3′ D1′ D0′ DON’T CARE
17037- Figure 2. SPI Timing Diagram
PACKAGE CHARACTERISTICS Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input Side to High-Side Output)1 RI-O 1012 Ω Capacitance (Input Side to High-Side Output)1 CI-O 2.0 pF Input Capacitance CI 4.0 pF 1 The device is considered a 2-terminal device: Pin 1 through Pin 14 are shorted together, and Pin 15 through Pin 28 are shorted together. Rev. 0 | Page 8 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ELECTRICAL CHARACTERISTICS SPI TIMING SPECIFICATIONS SPI Timing Diagram PACKAGE CHARACTERISTICS REGULATORY INFORMATION INSULATION AND SAFETY RELATED SPECIFICATIONS DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION PCB LAYOUT SPI AND EEPROM OPERATION SPI Programming USER REGISTER MAP USER REGISTER BITS OFFSET_2[5:0] Bits GAIN_2[5:0] Bits OFFSET_1[5:0] Bits GAIN_1[5:0] Bits CONFIGURATION REGISTER BITS OT_FAULT_OP Bit OT_FAULT_SEL Bit OC_TIME_OP Bit OC_2LEV_OP Bit LOW_T_OP Bit OC_BLANK_OP Bit tBLANK[3:0] Bits ECC_OFF_OP Bit T_RAMP_OP Bit PWM_OSC CONTROL REGISTER BITS ECC2_DBL_ERR Bit ECC2_SNG_ERR Bit ECC1_DBL_ERR Bit ECC1_SNG_ERR Bit PROG_BUSY Bit SIM_TRIM Bit SPI SAFETY PROPAGATION DELAY RELATED PARAMETERS PROTECTION FEATURES Primary Side UVLO Fault Reporting Overcurrent Detection High Speed, Two-Level Turn Off Miller Clamp Thermal Shutdown ASC Pin Functionality Isolated Temperature Sensor Low Temperature Operation Mode FAULTB Pin DRIVER_FAULTB Pin UVLO_FAULTB Pin VDD2 UVLO Fault UVLO_FAULTB Fault, Gate Low Dead Time Control DRIVER_FAULTB Fault, Dead Time Fault Power Dissipation INSULATION LIFETIME DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY TYPICAL APPLICATION CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS
SPI timing specifications are guaranteed by design. Al devices are production tested with 200 kHz SPI communication.
Table 2. Parameter Description Min Typ Max Unit
tS Time to first clock edge 8 µs tDS Set period 1 µs tDH Hold period 1 µs tCLK Clock period 5 µs tH Release time 8 µs tHIGH Clock time high 100 ns tLOW Clock time low 100 ns tOV Output valid time 240 ns
SPI Timing Diagram t t DS HIGH tCLK t t t t S DH LOW H UVLO_FAULT CS SCLK DON’T CARE DON’T CARE MOSI DON’T CARE MBZ RW0 A1 A0 MBZ MBZ MBZ MBZ D23 D5 D4 D3 D1 D0 DON’T CARE tOV
002
MISO HIGH-Z 0 RW0′ A1′ A0′ 0 0 0 0 D23′ D5′ D4′ D3′ D1′ D0′ DON’T CARE
17037- Figure 2. SPI Timing Diagram
PACKAGE CHARACTERISTICS Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input Side to High-Side Output)1 RI-O 1012 Ω Capacitance (Input Side to High-Side Output)1 CI-O 2.0 pF Input Capacitance CI 4.0 pF 1 The device is considered a 2-terminal device: Pin 1 through Pin 14 are shorted together, and Pin 15 through Pin 28 are shorted together. Rev. 0 | Page 8 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ELECTRICAL CHARACTERISTICS SPI TIMING SPECIFICATIONS SPI Timing Diagram PACKAGE CHARACTERISTICS REGULATORY INFORMATION INSULATION AND SAFETY RELATED SPECIFICATIONS DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION PCB LAYOUT SPI AND EEPROM OPERATION SPI Programming USER REGISTER MAP USER REGISTER BITS OFFSET_2[5:0] Bits GAIN_2[5:0] Bits OFFSET_1[5:0] Bits GAIN_1[5:0] Bits CONFIGURATION REGISTER BITS OT_FAULT_OP Bit OT_FAULT_SEL Bit OC_TIME_OP Bit OC_2LEV_OP Bit LOW_T_OP Bit OC_BLANK_OP Bit tBLANK[3:0] Bits ECC_OFF_OP Bit T_RAMP_OP Bit PWM_OSC CONTROL REGISTER BITS ECC2_DBL_ERR Bit ECC2_SNG_ERR Bit ECC1_DBL_ERR Bit ECC1_SNG_ERR Bit PROG_BUSY Bit SIM_TRIM Bit SPI SAFETY PROPAGATION DELAY RELATED PARAMETERS PROTECTION FEATURES Primary Side UVLO Fault Reporting Overcurrent Detection High Speed, Two-Level Turn Off Miller Clamp Thermal Shutdown ASC Pin Functionality Isolated Temperature Sensor Low Temperature Operation Mode FAULTB Pin DRIVER_FAULTB Pin UVLO_FAULTB Pin VDD2 UVLO Fault UVLO_FAULTB Fault, Gate Low Dead Time Control DRIVER_FAULTB Fault, Dead Time Fault Power Dissipation INSULATION LIFETIME DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY TYPICAL APPLICATION CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS
