Datasheet ADAR7251 (Analog Devices) - 5

Data Sheet ADAR7251 SPECIFICATIONS ANALOG CHANNEL
AVDDx = 3.3 V, DVDDx = 1.8 V, IOVDDx = 3.3 V, VREF = 1.5 V internal/external reference, fSAMPLE = 1.2 MSPS, TAMB = −40°C to +125°C, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE Input Referred Noise Spectral Density Frequency = 100 Hz Gain = 9 dB 44.7 nV/√Hz Gain = 15 dB 23.6 nV/√Hz Gain = 21 dB 15 nV/√Hz Gain = 27 dB 12 nV/√Hz Gain = 33 dB 11.3 nV/√Hz Gain = 39 dB 10.9 nV/√Hz Gain = 45 dB 10.8 nV/√Hz Frequency = 1 kHz Gain = 9 dB 16 nV/√Hz Gain = 15 dB 8.7 nV/√Hz Gain = 21 dB 5.4 nV/√Hz Gain = 27 dB 4.3 nV/√Hz Gain = 33 dB 4 nV/√Hz Gain = 39 dB 3.86 nV/√Hz Gain = 45 dB 3.83 nV/√Hz Frequency = 100 kHz Gain = 9 dB 9.7 nV/√Hz Gain = 15 dB 5.2 nV/√Hz Gain = 21 dB 3.3 nV/√Hz Gain = 27 dB 2.67 nV/√Hz Gain = 33 dB 2.5 nV/√Hz Gain = 39 dB 2.44 nV/√Hz Gain = 45 dB 2.4 nV/√Hz Equalizer Corner Frequency Setting 1 EQ00 54 kHz Setting 2 EQ01 45 kHz Setting 3 EQ10 37 kHz Setting 4 EQ11 32 kHz Signal to Noise Ratio (SNR) No input signal and reference to 0 dBFS 88 94 dB Spurious-Free Dynamic Range (SFDR) At −3 dBFS input, 100 kHz 68 82 dB Total Harmonic Distortion Plus Noise (THD + N) At −3 dBFS input, 100 kHz −80 −66 dB At −1 dBFS input, 100 kHz −77 −62 dB Channel to Channel Crosstalk At 50 kHz, −3 dBFS input −94 −89 dB Interchannel Gain Mismatch −0.5 0 +0.5 dB Interchannel Phase Mismatch 0.04 Degrees DC Offset −72 dBFS Power Supply Rejection Ripple = 100 mV rms on AVDDx at 65 dB 1 kHz Rev. 0 | Page 5 of 72 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Analog Channel Digital Input/Output Power Supply Digital Filter SPI Port Timing Serial/Peripheral Parallel Interface (PPI) Port Timing Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Low Speed Ramp Radar Analog Front End Main Channel Overview Σ-∆ Modulation and Digital Filtering Differential Input Configuration High-Pass Filter (HPF) Low-Pass Filter (LPF) Input Routing Equalizer (EQ) Using LNA/PGA, EQ, or the Input Capacitor Reference Auxiliary ADC Power Supply LDO Clock Requirements Crystal Oscillator PLL Integer Mode Fractional Mode PLL Lock Acquisition GPIO ADC Data Port ADC Serial Mode ADC Serial Master Mode ADC Serial Master Mode with ADC Serial Slave ADC PPI (Byte Wide Mode) ADC PPI Nibble Wide Mode DAQ Mode Using Multiple ADAR7251 Devices for Systems with More Than Four Channels Device Address R/ Register Address Data Bytes CRC PCB Layout Guidelines Register Summary Register Details Clock Control Register PLL Denominator Register PLL Numerator Register PLL Control Register PLL Status Register Master Enable Switch Register ADC Enable Register Power Enable Register Clear the ASIL errors Register Selects Which Errors to Mask Register ASIL Error Flag Register ASIL Error Code Register CRC Value, Bits[7:0] Register CRC Value Register Start Calculating the CRC Value of the Register Map Content Register Register Map CRC Calculation Done Register Register Map CRC Value, Bits[7:0] Register Register Map CRC Value, Bits[15:8] Register Low Noise Amplifier Gain Control Register Programmable Gain Amplifier Gain Control Register Signal Path for ADC 1 Through ADC 4 Register Decimator Rate Control Register High Pass Filter Control Register DAQ Mode Control Register Decimator Truncate Control Register Serial Output Port Control Register Parallel Port Control Register ADC Digital Output Mode Register Auxiliary ADC Read Value Registers Auxiliary ADC Sample Rate Selection Register Auxiliary ADC Mode Register MPx Pin Modes Registers MP Write Value Registers MP Read Value Registers SPI_CLK Pin Drive Strength and Slew Rate Register SPI_MISO Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register SPI_MOSI Pin Drive Strength and Slew Rate Register ADDR15 Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register FS_ADC Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register SCLK_ADC Pin Drive Strength and Slew Rate Register ADC_DOUTx Pins Drive Strength and Slew Rate Registers DATA_READY Pin Drive Strength and Slew Rate Register XTAL Enable and Drive Register ADC Test Register Digital Filter Sync Enable Register CRC Enable/Disable Register Typical Application Circuit Outline Dimensions Ordering Guide Automotive Products