Datasheet AD7176-2 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | 24-Bit, 250 kSPS Sigma Delta ADC with 20 µs Settling |
| Pages / Page | 6 / 1 — Key Sheet. AD7176-2 |
| File Format / Size | PDF / 159 Kb |
| Document Language | English |
Key Sheet. AD7176-2
Model Line for this Datasheet
Text Version of Document
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Key Sheet AD7176-2 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Highlights of the AD7176-2— 24-Bit, 250 kSPS Sigma-Delta ADC with 20 µs Settling AVDD1 AVDD2 REGCAPA REF– REF+ REFOUT IOVDD REGCAPD BUFFERED 1.8V 1.8V PRECISION LDO LDO REFERENCE INT REF AIN0 CS AIN1 SCLK SERIAL Σ-Δ ADC DIGITAL INTERFACE DIN AIN2 FILTER AND CONTROL DOUT/RDY AIN3 SYNC/ERROR I/O XTAL AND INTERNAL CLOCK OSCILLATOR AIN4 CONTROL CIRCUITRY CROSSPOINT AD7176-2 MULTIPLEXER
001
AVSS GPIO0 GPIO1 XTAL1 CLKIO/XTAL2 DGND
11266- Figure 1. Functional Block Diagram
GENERAL DESCRIPTION FEATURES AND BENEFITS
This key sheet1 provides users with an overview of the AD7176-2. The AD7176-2 offers the fol owing features and benefits: Key attributes of the part include the fol owing: • Simultaneous 50 Hz and 60 Hz rejection at 27 SPS ODR • Designed for process control: PLC/DCS modules, temperature • Internal oscillator adds functionality and reduces external and pressure measurement, medical and scientific multi- component count channel instrumentation, and chromatography. • Optional split supply operation of ±2.5 V with AVDD1 • Fast settling, highly accurate, high resolution, multiplexed, referenced to AVSS 24-bit Sigma-Delta (Σ-Δ) ADC for low bandwidth input • System offset and gain errors can be corrected on a per signals with a fully flexible output data rate (ODR) between channel basis 5 SPS and 250 kSPS. • Low noise performance across the ODR range • Combines two fully differential or four pseudo differential • Fully compatible with SPI, QSPI™, MICROWIRE®, and DSP input channels, selected via the integrated crosspoint • Sinc5 + Sinc1, Sinc3, and enhanced 50 Hz and 60 Hz multiplexer. rejection digital filter options (see the Frequently Asked • With an ODR of 250 kSPS, the AD7176-2 boasts an rms Questions section for more information) noise of 9.7 µV when operating with the default Sinc5 + • SPI configuration control Sinc1 filter. • 3- or 4-wire serial digital interface (Schmitt trigger on SCLK) • User friendly, with the part being fully configurable over a 4-wire serial interface. • Available in a small 24-lead TSSOP package, allowing a reduced board size. 1 This document provides users with an overview of the AD7176-2; it is not a notice of performance or intent. Refer to the AD7176-2 data sheet for performance and more specific information about this product.
Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2013 Analog Devices, Inc. All rights reserved.
Document Outline General Description Features and Benefits Key Characteristics Fundamental Specifications Noise Operating the AD7176-2 Data Interface Accessing the ADC Register Map ADC and Interface Mode Configuration ADC Mode Register Interface Mode Register Data Modes Continuous Conversion Mode (Default) Continuous Read Mode Single Conversion Mode Typical Application Diagram Frequently Asked Questions Learn More and Start Designing Compatible Devices Package Diagram Getting Started
Key Sheet AD7176-2 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Highlights of the AD7176-2— 24-Bit, 250 kSPS Sigma-Delta ADC with 20 µs Settling AVDD1 AVDD2 REGCAPA REF– REF+ REFOUT IOVDD REGCAPD BUFFERED 1.8V 1.8V PRECISION LDO LDO REFERENCE INT REF AIN0 CS AIN1 SCLK SERIAL Σ-Δ ADC DIGITAL INTERFACE DIN AIN2 FILTER AND CONTROL DOUT/RDY AIN3 SYNC/ERROR I/O XTAL AND INTERNAL CLOCK OSCILLATOR AIN4 CONTROL CIRCUITRY CROSSPOINT AD7176-2 MULTIPLEXER
001
AVSS GPIO0 GPIO1 XTAL1 CLKIO/XTAL2 DGND
11266- Figure 1. Functional Block Diagram
GENERAL DESCRIPTION FEATURES AND BENEFITS
This key sheet1 provides users with an overview of the AD7176-2. The AD7176-2 offers the fol owing features and benefits: Key attributes of the part include the fol owing: • Simultaneous 50 Hz and 60 Hz rejection at 27 SPS ODR • Designed for process control: PLC/DCS modules, temperature • Internal oscillator adds functionality and reduces external and pressure measurement, medical and scientific multi- component count channel instrumentation, and chromatography. • Optional split supply operation of ±2.5 V with AVDD1 • Fast settling, highly accurate, high resolution, multiplexed, referenced to AVSS 24-bit Sigma-Delta (Σ-Δ) ADC for low bandwidth input • System offset and gain errors can be corrected on a per signals with a fully flexible output data rate (ODR) between channel basis 5 SPS and 250 kSPS. • Low noise performance across the ODR range • Combines two fully differential or four pseudo differential • Fully compatible with SPI, QSPI™, MICROWIRE®, and DSP input channels, selected via the integrated crosspoint • Sinc5 + Sinc1, Sinc3, and enhanced 50 Hz and 60 Hz multiplexer. rejection digital filter options (see the Frequently Asked • With an ODR of 250 kSPS, the AD7176-2 boasts an rms Questions section for more information) noise of 9.7 µV when operating with the default Sinc5 + • SPI configuration control Sinc1 filter. • 3- or 4-wire serial digital interface (Schmitt trigger on SCLK) • User friendly, with the part being fully configurable over a 4-wire serial interface. • Available in a small 24-lead TSSOP package, allowing a reduced board size. 1 This document provides users with an overview of the AD7176-2; it is not a notice of performance or intent. Refer to the AD7176-2 data sheet for performance and more specific information about this product.
Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2013 Analog Devices, Inc. All rights reserved.
Document Outline General Description Features and Benefits Key Characteristics Fundamental Specifications Noise Operating the AD7176-2 Data Interface Accessing the ADC Register Map ADC and Interface Mode Configuration ADC Mode Register Interface Mode Register Data Modes Continuous Conversion Mode (Default) Continuous Read Mode Single Conversion Mode Typical Application Diagram Frequently Asked Questions Learn More and Start Designing Compatible Devices Package Diagram Getting Started
