Datasheet AD7176-2 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 24-Bit, 250 kSPS Sigma Delta ADC with 20 µs Settling |
| Pages / Page | 6 / 4 — AD7176-2. Key Sheet. DIN. DOUT/RDY. DATA. REQUEST. SCLK. Single … |
| File Format / Size | PDF / 159 Kb |
| Document Language | English |
AD7176-2. Key Sheet. DIN. DOUT/RDY. DATA. REQUEST. SCLK. Single Conversion Mode. TYPICAL APPLICATION DIAGRAM. GPIO0 AND GPIO1
Model Line for this Datasheet
Text Version of Document
AD7176-2 Key Sheet
DOUT/RDY returns high until the next conversion is available. If several channels are enabled, the ADC automatical y In this mode, the data can be read only once. If multiple ADC sequences through the enabled channels and performs a channels are enabled, each channel is output in turn, with the conversion on each channel. When a conversion is started, status bits being appended to the data if DATA_STAT is set in DOUT/RDY goes high and remains high until a valid conversion the interface mode register. The status register indicates the is available and CS is low. As soon as a conversion is available, channel to which the conversion corresponds. DOUT/RDY goes low. The ADC then selects the next channel
CS
and begins another conversion. The user can read the present conversion while the next conversion is being performed. The two LSBs of the status register indicate the channel to which the
DIN
conversion corresponds.
CS DOUT/RDY DATA DATA DATA DATA REQUEST
007
DIN SCLK
11266- Figure 5. Continuous Read Mode
DATA DOUT/RDY Single Conversion Mode
In single conversion mode, the AD7176-2 performs a single 005
SCLK
conversion and is placed in standby mode after the conversion 11266- is complete. DOUT/RDY goes low to indicate the completion of a Figure 6. Single Conversion Mode conversion. When the data-word has been read from the data register, DOUT/RDY goes high. The data register can be read several times, if required, even when DOUT/RDY has gone high.
TYPICAL APPLICATION DIAGRAM GPIO0 AND GPIO1 OUTPUT HIGH = AVDD GPIO0 OUTPUT LOW = AVSS GPIO1 FOR SINGLE SUPPLY CASE OUTPUT HIGH = 5V OUTPUT LOW = GND 16MHz 19 20 GPIO0 GPIO1 CX1 CX2 OPTIONAL EXTERNAL XTAL1 9 CRYSTAL CIRCUITRY 21 AIN0 CAPACITORS IN0 CLKI0/XTAL2 10 CLKIN OPTIONAL DOUT/RDY 11 DOUT/RDY EXTERNAL CLOCK 22 AIN1 INPUT IN1 12 DIN DIN IN2 13 SCLK 23 AIN2 SCLK CS 14 CS IN3 24 AIN3 SYNC/ERROR 15 SYNC/ERROR AD7176-2 IOVDD IN4 AIN4 1 IOVDD 16 AIN4 0.1µF DGND 17 1 3 REGCAPD 18 VIN TP NC 0.1µF 1µF AVDD1 2 V NC 7 IN 4.7µF 0.1µF AVDD1 7 ADR445BRZ 0.1µF AVDD2 4 GND VOUT 6 3 REF+ AVDD2 8 0.1µF 4.7µF 0.1µF TRIM TP 0.1µF 5 8 2 REF– REGCAPA 5 4 REFOUT 2.5V REFERENCE AVSS 0.1µF 1µF 0.1µF OUTPUT 6
006 11266- Figure 7. Typical Application Diagram Rev. 0 | Page 4 of 6 Document Outline General Description Features and Benefits Key Characteristics Fundamental Specifications Noise Operating the AD7176-2 Data Interface Accessing the ADC Register Map ADC and Interface Mode Configuration ADC Mode Register Interface Mode Register Data Modes Continuous Conversion Mode (Default) Continuous Read Mode Single Conversion Mode Typical Application Diagram Frequently Asked Questions Learn More and Start Designing Compatible Devices Package Diagram Getting Started
DOUT/RDY returns high until the next conversion is available. If several channels are enabled, the ADC automatical y In this mode, the data can be read only once. If multiple ADC sequences through the enabled channels and performs a channels are enabled, each channel is output in turn, with the conversion on each channel. When a conversion is started, status bits being appended to the data if DATA_STAT is set in DOUT/RDY goes high and remains high until a valid conversion the interface mode register. The status register indicates the is available and CS is low. As soon as a conversion is available, channel to which the conversion corresponds. DOUT/RDY goes low. The ADC then selects the next channel
CS
and begins another conversion. The user can read the present conversion while the next conversion is being performed. The two LSBs of the status register indicate the channel to which the
DIN
conversion corresponds.
CS DOUT/RDY DATA DATA DATA DATA REQUEST
007
DIN SCLK
11266- Figure 5. Continuous Read Mode
DATA DOUT/RDY Single Conversion Mode
In single conversion mode, the AD7176-2 performs a single 005
SCLK
conversion and is placed in standby mode after the conversion 11266- is complete. DOUT/RDY goes low to indicate the completion of a Figure 6. Single Conversion Mode conversion. When the data-word has been read from the data register, DOUT/RDY goes high. The data register can be read several times, if required, even when DOUT/RDY has gone high.
TYPICAL APPLICATION DIAGRAM GPIO0 AND GPIO1 OUTPUT HIGH = AVDD GPIO0 OUTPUT LOW = AVSS GPIO1 FOR SINGLE SUPPLY CASE OUTPUT HIGH = 5V OUTPUT LOW = GND 16MHz 19 20 GPIO0 GPIO1 CX1 CX2 OPTIONAL EXTERNAL XTAL1 9 CRYSTAL CIRCUITRY 21 AIN0 CAPACITORS IN0 CLKI0/XTAL2 10 CLKIN OPTIONAL DOUT/RDY 11 DOUT/RDY EXTERNAL CLOCK 22 AIN1 INPUT IN1 12 DIN DIN IN2 13 SCLK 23 AIN2 SCLK CS 14 CS IN3 24 AIN3 SYNC/ERROR 15 SYNC/ERROR AD7176-2 IOVDD IN4 AIN4 1 IOVDD 16 AIN4 0.1µF DGND 17 1 3 REGCAPD 18 VIN TP NC 0.1µF 1µF AVDD1 2 V NC 7 IN 4.7µF 0.1µF AVDD1 7 ADR445BRZ 0.1µF AVDD2 4 GND VOUT 6 3 REF+ AVDD2 8 0.1µF 4.7µF 0.1µF TRIM TP 0.1µF 5 8 2 REF– REGCAPA 5 4 REFOUT 2.5V REFERENCE AVSS 0.1µF 1µF 0.1µF OUTPUT 6
006 11266- Figure 7. Typical Application Diagram Rev. 0 | Page 4 of 6 Document Outline General Description Features and Benefits Key Characteristics Fundamental Specifications Noise Operating the AD7176-2 Data Interface Accessing the ADC Register Map ADC and Interface Mode Configuration ADC Mode Register Interface Mode Register Data Modes Continuous Conversion Mode (Default) Continuous Read Mode Single Conversion Mode Typical Application Diagram Frequently Asked Questions Learn More and Start Designing Compatible Devices Package Diagram Getting Started
