Datasheet AD8285 (Analog Devices) - 8

AD8285 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DRV DRV DD33 DD33 NC DV NC NC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 DV NC 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 NC 1 54 NC PIN 1 DSYNC 2 INDICATOR 53 TEST4 PDWN 3 52 DVDD18CLK DVDD18 4 51 CLK+ SCLK 5 50 CLK– SDIO 6 49 DVDD33CLK CS 7 48 AVDD33REF AUX 8 47 VREF MUXA 9 AD8285 46 RBIAS ZSEL 10 TOP VIEW 45 BAND TEST1 11 (Not to Scale) 44 APOUT TEST2 12 43 ANOUT DVDD33SPI 13 42 TEST3 AVDD18 14 41 AVDD18ADC AVDD33A 15 40 AVDD18 INA– 16 39 INADC+ INA+ 17 38 INADC– NC 18 37 NC 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 – – – NC NC B C D 33B NC NC NC NC NC IN INB+ 33C IN INC+ 33D IN IND+ DD33 DD33 DD DD DD AV AV AV AV AV NOTES
003
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
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2. TIE THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE TO THE ANALOG/DIGITAL GROUND PLANE.
119 Figure 3. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
0 EPAD Exposed Pad. Tie the exposed pad on the bottom of the package to the analog/digital ground plane. 1 NC No Connect. Do not connect to this pin. 2 DSYNC Data Output Synchronization. 3 PDWN Full Power Down. Logic high overrides the SPI and powers down the device. Logic low allows selection of the power down option through the SPI. 4 DVDD18 1.8 V Digital Supply. 5 SCLK Serial Clock. 6 SDIO Serial Data Input/Output. 7 CS Chip Select Bar. 8 AUX Auxiliary. A logic high on AUX switches the AUX channel (INADC+/INADC−) to the ADC. The AUX pin has a higher priority than the MUXA pin. 9 MUXA Channel A Select. Logic high forces to Channel A unless AUX is asserted. 10 ZSEL Input Impedance Select. Logic high overrides the SPI and sets the input impedance to 200 kΩ. Logic low allows selection of the input impedance through the SPI. 11 TEST1 Test. Do not use the TEST1 pin; tie it to ground. 12 TEST2 Test. Do not use the TEST2 pin; tie it to ground. 13 DVDD33SPI 3.3 V Digital Supply for SPI Port. 14 AVDD18 1.8 V Analog Supply. 15 AVDD33A 3.3 V Analog Supply for Channel A. 16 INA− Negative LNA Analog Input for Channel A. 17 INA+ Positive LNA Analog Input for Channel A. 18 NC No Connect. Do not connect to this pin. 19 NC No Connect. Do not connect to this pin. 20 NC No Connect. Do not connect to this pin. 21 AVDD33B 3.3 V Analog Supply for Channel B. 22 INB− Negative LNA Analog Input for Channel B. 23 INB+ Positive LNA Analog Input for Channel B. Rev. B | Page 8 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION RADAR RECEIVE PATH AFE CHANNEL OVERVIEW Low Noise Amplifier (LNA) Recommendation Antialiasing Filter (AAF) Mux and Mux Controller ADC CLOCK INPUT CONSIDERATIONS CLOCK DUTY CYCLE CONSIDERATIONS CLOCK JITTER CONSIDERATIONS SDIO PIN SCLK PIN CS\ PIN RBIAS PIN VOLTAGE REFERENCE POWER AND GROUND RECOMMENDATIONS EXPOSED PADDLE THERMAL HEAT SLUG RECOMMENDATIONS SERIAL PERIPHERAL INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE LOGIC LEVELS RESERVED LOCATIONS DEFAULT VALUES APPLICATION DIAGRAMS OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS