Datasheet AD9670 (Analog Devices) - 4

link to page 4 link to page 6
AD9670 Data Sheet SPECIFICATIONS AC SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (0°C to 85°C), fIN = 5 MHz, local oscillator (LO) band mode, RS = 50 Ω, RFB = ∞ (unterminated), LNA gain = 21.6 dB, LNA bias = midhigh, PGA gain = 27 dB, analog gain control, VGAIN = (GAIN+) − (GAIN−) = 1.6 V, antialiasing filter, low-pass filter (LPF) cutoff = fSAMPLE/3 in Mode I/Mode II, antialiasing filter LPF cutoff = fSAMPLE /4.5 in Mode III/Mode IV, high-pass filter (HPF) cutoff = LPF cutoff/12.00, Mode I = fSAMPLE = 40 MSPS, Mode II = fSAMPLE = 65 MSPS, Mode III = fSAMPLE = 80 MSPS, Mode IV = 125 MSPS, radio frequency (RF) decimator bypassed, digital demod- ulator and baseband decimator bypassed, digital high-pass filter bypassed, low power LVDS mode, unless otherwise noted. All gain setting options are listed, which can be configured via SPI registers, and all power supply currents and power dissipations are listed for the four mode settings (Mode I, Mode II, Mode III, and Mode IV), respectively, via slashes in Table 1.
Table 1. Parameter1 Test Conditions/Comments Min Typ Max Unit
LNA CHARACTERISTICS Gain Single-ended input to differential output 15.6/17.9/21.6 dB Single-ended input to single-ended output 9.6/11.9/15.6 dB 0.1 dB Input Compression Point LNA gain = 15.6 dB 1.00 V p-p LNA gain = 17.9 dB 0.75 V p-p LNA gain = 21.6 dB 0.45 V p-p 1 dB Input Compression Point LNA gain = 15.6 dB 1.20 V p-p LNA gain = 17.9 dB 0.90 V p-p LNA gain = 21.6 dB 0.60 V p-p Input Common Mode (LI-x, LG-x) 2.2 V Output Common Mode LO-x Switch off High-Z Ω Switch on 1.5 V LOSW-x Switch off High-Z Ω Switch on 1.5 V Input Resistance (LI-x) RFB = 300 Ω 50 Ω RFB = 1350 Ω 200 Ω 6 kΩ Input Capacitance (LI-x) 20 pF Input Noise Voltage RS = 0 Ω LNA gain = 15.6 dB 0.83 nV/√Hz LNA gain = 17.9 dB 0.82 nV/√Hz LNA gain = 21.6 dB 0.78 nV/√Hz Input Noise Current 2.6 pA/√Hz FULL CHANNEL (TGC) CHARACTERISTICS Antialiasing Filter Low-Pass Cutoff −3 dB, programmable, low band mode 8 18 MHz −3 dB, programmable, high band mode 13.5 30 MHz In Range Antialiasing Filter ±10 % Bandwidth Tolerance Group Delay Variation f = 1 MHz to 18 MHz, VGAIN = −1.6 V to +1.6 V ±350 ps Input Referred Noise Voltage LNA gain = 15.6 dB 0.96 nV/√Hz LNA gain = 17.9 dB 0.90 nV/√Hz LNA gain = 21.6 dB 0.82 nV/√Hz Noise Figure RS = 50 Ω Active Termination Matched LNA gain = 15.6 dB, RFB = 150 Ω 5.6 dB LNA gain = 17.9 dB, RFB = 200 Ω 4.8 dB LNA gain = 21.6 dB, RFB = 300 Ω 3.8 dB Unterminated LNA gain = 15.6 dB 3.2 dB LNA gain = 17.9 dB 2.9 dB LNA gain = 21.6 dB 2.6 dB Correlated Noise Ratio No signal, correlated/uncorrelated −30 dB Output Offset −100 +100 LSB Rev. A | Page 4 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ADC Timing Diagram CW Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CHARACTERISTICS CW DOPPLER MODE CHARACTERISTICS THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter Antialiasing Filter/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control Digital Outputs and Timing Output Zero Stuffing SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin General-Purpose Output Pins Chip Address Pins ANALOG TEST SIGNAL GENERATION CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter DIGITAL DEMODULATOR/DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband Antialiasing Filter and Decimate by 2 High-Pass Filter BASEBAND DEMODULATOR AND DECIMATOR Numerically Controlled Oscillator Decimation Filter Coefficient Memory DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator Filter Coefficients DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED STARTUP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Transfer (Register 0x0FF) Profile Index and Manual TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE