Datasheet AD9670 (Analog Devices) - 5

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Data Sheet AD9670 Parameter1 Test Conditions/Comments Min Typ Max Unit
Signal-to-Noise Ratio (SNR) fIN = 5 MHz at −12 dBFS, VGAIN = −1.6 V 69 dBFS fIN = 5 MHz at −1 dBFS 59 dBFS Close In SNR fIN = 3.5 MHz at −1 dBFS, VGAIN = 0 V, 1 kHz offset −130 dBc/√Hz Second Harmonic fIN = 5 MHz at −12 dBFS, VGAIN = −1.6 V −70 dBc fIN = 5 MHz at −1 dBFS, VGAIN = 1.6 V −62 dBc Third Harmonic fIN = 5 MHz at −12 dBFS, VGAIN = −1.6 V −61 dBc fIN = 5 MHz at −1 dBFS, VGAIN = 1.6 V −55 dBc Two-Tone Intermodulation fRF1 = 5.015 MHz, fRF2 = 5.020 MHz, ARF1 = −1 dBFS, −54 dBc Distortion (IMD3) ARF2 = −21 dBFS, VGAIN = 1.6 V, IMD3 relative to ARF2 Channel-to-Channel Crosstalk fIN1 = 5.0 MHz at −1 dBFS −60 dB Overrange condition2 −55 dB GAIN ACCURACY TA = 25°C Gain Law Conformance Error −1.6 < VGAIN < −1.28 V 0.4 dB −1.28 V < VGAIN ≤ +1.28 V −1.3 +1.3 dB 1.28 V < VGAIN < 1.6 V −0.5 dB Linear Gain Error VGAIN = 0 V, normalized for ideal antialiasing filter loss −1.3 +1.3 dB Channel-to-Channel Matching −1.28 V < VGAIN < +1.28 V, 1 σ 0.1 dB PGA Gain 21/24/27/30 dB GAIN CONTROL INTERFACE Control Range Differential −1.6 +1.6 V Control Common Mode GAIN+, GAIN− 0.7 0.8 0.9 V Input Impedance GAIN+, GAIN− 10 MΩ Gain Range 45 dB Scale Factor Analog 14 dB/V Digital step size 3.5 dB Response Time Analog 45 dB change 750 ns CW DOPPLER MODE LO Frequency fLO = fMLO/M 1 10 MHz Phase Resolution Per channel, 4LO3 mode 45 Degrees Per channel, 8LO mode, 16LO mode 22.5 Degrees Output DC Bias (Single-Ended) CWI+, CWI−, CWQ+, and CWQ− AVDD2/2 V Output AC Current Range Per CWI+, CWI−, CWQ+, and CWQ−, each channel ±2.2 ±2.5 mA enabled (2 fLO and baseband signal) Transconductance (Differential) Demodulated IOUT/VIN, per CWI+, CWI−, CWQ+, and CWQ− LNA gain = 15.6 dB 3.3 mA/V LNA gain = 17.9 dB 4.3 mA/V LNA gain = 21.6 dB 6.6 mA/V Input Referred Noise Voltage RS = 0 Ω, RFB = ∞ LNA gain = 15.6 dB 1.6 nV/√Hz LNA gain = 17.9 dB 1.3 nV/√Hz LNA gain = 21.6 dB 1.0 nV/√Hz Noise Figure RS = 50 Ω, RFB = ∞ LNA gain = 15.6 dB 5.7 dB LNA gain = 17.9 dB 4.5 dB LNA gain = 21.6 dB 3.4 dB Dynamic Range RS = 0 Ω, RFB = ∞ LNA gain = 15.6 dB 164 dBFS/√Hz LNA gain = 17.9 dB 162 dBFS/√Hz LNA gain = 21.6 dB 160 dBFS/√Hz Close In SNR −3 dBFS input, fRF = 2.5 MHz, fLO = 40 MHz, 1 kHz 156 dBc/√Hz offset, 16LO mode, 1 channel enabled −3 dBFS input, fRF = 2.5 MHz, fLO = 40 MHz, 1 kHz 161 dBc/√Hz offset, 16LO mode, 8 channels enabled Rev. A | Page 5 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ADC Timing Diagram CW Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CHARACTERISTICS CW DOPPLER MODE CHARACTERISTICS THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter Antialiasing Filter/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control Digital Outputs and Timing Output Zero Stuffing SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin General-Purpose Output Pins Chip Address Pins ANALOG TEST SIGNAL GENERATION CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter DIGITAL DEMODULATOR/DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband Antialiasing Filter and Decimate by 2 High-Pass Filter BASEBAND DEMODULATOR AND DECIMATOR Numerically Controlled Oscillator Decimation Filter Coefficient Memory DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator Filter Coefficients DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED STARTUP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Transfer (Register 0x0FF) Profile Index and Manual TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE