Datasheet AD6641 (Analog Devices)

250 MHz Bandwidth DPD Observation Receiver AD6641 FEATURES GENERAL DESCRIPTION SNR = 65.8 dBFS at fIN up to 250 MHz at 500 MSPS
The AD6641 is a 250 MHz bandwidth digital predistortion
ENOB of 10.5 bits at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
(DPD) observation receiver that integrates a 12-bit 500 MSPS
SFDR = 80 dBc at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
ADC, a 16k × 12 FIFO, and a multimode back end that allows
Excellent linearity
users to retrieve the data through a serial port (SPORT), the SPI
DNL = ±0.5 LSB typical, INL = ±0.6 LSB typical
interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVDS
Integrated 16k × 12 FIFO
port after being stored in the integrated FIFO memory. It is opti-
FIFO readback options
mized for outstanding dynamic performance and low power
12-bit parallel CMOS at 62.5 MHz
consumption and is suitable for use in telecommunications
6-bit DDR LVDS interface
applications such as a digital predistortion observation path
SPORT at 62.5 MHz
where wider bandwidths are desired. All necessary functions,
SPI at 25 MHz
including the sample-and-hold and voltage reference, are
High speed synchronization capability
included on the chip to provide a complete signal conversion
1 GHz full power analog bandwidth
solution.
Integrated input buffer
The on-chip FIFO allows small snapshots of time to be captured
On-chip reference, no external decoupling required
via the ADC and read back at a lower rate. This reduces the
Low power dissipation
constraints of signal processing by transferring the captured
695 mW at 500 MSPS
data at an arbitrary time and at a much lower sample rate. The
Programmable input voltage range
FIFO can be operated in several user-programmable modes. In
1.18 V to 1.6 V, 1.5 V nominal
the single capture mode, the ADC data is captured when sig-
1.9 V analog and digital supply operation
naled via the SPI port or the use of the external FILL± pins. In
1.9 V or 3.3 V SPI and SPORT operation
the continuous capture mode, the data is loaded continuously
Clock duty cycle stabilizer
into the FIFO and the FILL± pins are used to stop this operation.
Integrated data clock output with programmable clock and data alignment APPLICATIONS Wireless and wired broadband communications Communications test equipment Power amplifier linearization FUNCTIONAL BLOCK DIAGRAM FILL+ FILL– DUMP CLK+ CLOCK AND CONTROL CLK– PCLK+ PCLK– PARALLEL VIN+ PD[5:0]± IN DDR LVDS MODE FIFO AND OR PD[11:0] IN CMOS MODE ADC 16k × 12 SPORT VIN– OUTPUTS SP_SCLK SP_SDFS SP_SDO SPI CONTROL REFERENCE AND DATA FULL EMPTY
1 13-00
VREF SCLK, SDIO, AND CSB
098 Figure 1.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS SPI TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS SPI REGISTER MAP THEORY OF OPERATION FIFO OPERATION Single Capture Mode Fill Pin Timing Dump Pin Timing SPORT Master Mode (Single Capture) Fill Pulse (1) Empty Signal (2) Full Signal (3) Dump Signal (4)—Transition to High SCLK Signal (5) SDFS Signal (6) Dump Signal (7)—Transition to Low Empty Signal (8)—Transition to High Parallel Master Mode (Single Capture) Fill Pulse (1) Empty Signal (2) Full Signal (3) Dump Signal (4)—Transition to High PCLK± Signal (5) PD[11:0] Signal (6) Dump Signal (7)—Transition to Low Empty Signal (8)—Transition to High Continuous Capture Mode FIFO OUTPUT INTERFACES SPORT Interface Serial Data Frame (Serial Bus Master) CMOS Output Interface LVDS Output Interface ANALOG INPUT AND VOLTAGE REFERENCE VREF CONFIGURATION USING THE SPI OUTLINE DIMENSIONS ORDERING GUIDE