Datasheet AD6641 (Analog Devices) - 2
| Manufacturer | Analog Devices |
| Description | 250 MHz Bandwidth DPD Observation Receiver |
| Pages / Page | 28 / 2 — AD6641. TABLE OF CONTENTS. REVISION HISTORY. 4/11—Revision 0: Initial … |
| File Format / Size | PDF / 662 Kb |
| Document Language | English |
AD6641. TABLE OF CONTENTS. REVISION HISTORY. 4/11—Revision 0: Initial Version
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AD6641 TABLE OF CONTENTS
Features .. 1 Thermal Resistance .. 10 Applications... 1 ESD Caution.. 10 General Description ... 1 Pin Configurations and Function Descriptions ... 11 Functional Block Diagram .. 1 Typical Performance Characteristics ... 15 Revision History ... 2 Equivalent Circuits... 18 Product Highlights ... 3 SPI Register Map .. 20 Specifications... 4 Theory of Operation .. 23 DC Specifications ... 4 FIFO Operation .. 23 AC Specifications.. 5 FIFO Output Interfaces ... 26 Digital Specifications ... 6 Configuration Using the SPI... 27 Switching Specifications .. 7 Outline Dimensions ... 28 SPI Timing Requirements ... 8 Ordering Guide .. 28 Absolute Maximum Ratings.. 10
REVISION HISTORY 4/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS SPI TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS SPI REGISTER MAP THEORY OF OPERATION FIFO OPERATION Single Capture Mode Fill Pin Timing Dump Pin Timing SPORT Master Mode (Single Capture) Fill Pulse (1) Empty Signal (2) Full Signal (3) Dump Signal (4)—Transition to High SCLK Signal (5) SDFS Signal (6) Dump Signal (7)—Transition to Low Empty Signal (8)—Transition to High Parallel Master Mode (Single Capture) Fill Pulse (1) Empty Signal (2) Full Signal (3) Dump Signal (4)—Transition to High PCLK± Signal (5) PD[11:0] Signal (6) Dump Signal (7)—Transition to Low Empty Signal (8)—Transition to High Continuous Capture Mode FIFO OUTPUT INTERFACES SPORT Interface Serial Data Frame (Serial Bus Master) CMOS Output Interface LVDS Output Interface ANALOG INPUT AND VOLTAGE REFERENCE VREF CONFIGURATION USING THE SPI OUTLINE DIMENSIONS ORDERING GUIDE
AD6641 TABLE OF CONTENTS
Features .. 1 Thermal Resistance .. 10 Applications... 1 ESD Caution.. 10 General Description ... 1 Pin Configurations and Function Descriptions ... 11 Functional Block Diagram .. 1 Typical Performance Characteristics ... 15 Revision History ... 2 Equivalent Circuits... 18 Product Highlights ... 3 SPI Register Map .. 20 Specifications... 4 Theory of Operation .. 23 DC Specifications ... 4 FIFO Operation .. 23 AC Specifications.. 5 FIFO Output Interfaces ... 26 Digital Specifications ... 6 Configuration Using the SPI... 27 Switching Specifications .. 7 Outline Dimensions ... 28 SPI Timing Requirements ... 8 Ordering Guide .. 28 Absolute Maximum Ratings.. 10
REVISION HISTORY 4/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS SPI TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS SPI REGISTER MAP THEORY OF OPERATION FIFO OPERATION Single Capture Mode Fill Pin Timing Dump Pin Timing SPORT Master Mode (Single Capture) Fill Pulse (1) Empty Signal (2) Full Signal (3) Dump Signal (4)—Transition to High SCLK Signal (5) SDFS Signal (6) Dump Signal (7)—Transition to Low Empty Signal (8)—Transition to High Parallel Master Mode (Single Capture) Fill Pulse (1) Empty Signal (2) Full Signal (3) Dump Signal (4)—Transition to High PCLK± Signal (5) PD[11:0] Signal (6) Dump Signal (7)—Transition to Low Empty Signal (8)—Transition to High Continuous Capture Mode FIFO OUTPUT INTERFACES SPORT Interface Serial Data Frame (Serial Bus Master) CMOS Output Interface LVDS Output Interface ANALOG INPUT AND VOLTAGE REFERENCE VREF CONFIGURATION USING THE SPI OUTLINE DIMENSIONS ORDERING GUIDE
