Datasheet AD6641 (Analog Devices) - 10

AD6641 ABSOLUTE MAXIMUM RATINGS Table 6.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
Parameter Rating
rating only; functional operation of the device at these or any Electrical other conditions above those indicated in the operational AVDD to AGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute DRVDD to DRGND −0.3 V to +2.0 V maximum rating conditions for extended periods may affect AGND to DRGND −0.3 V to +0.3 V device reliability. AVDD to DRVDD −2.0 V to +2.0 V SPI_VDDIO to AVDD −2.0 V to +2.0 V
THERMAL RESISTANCE
SPI_VDDIO to DRVDD −2.0 V to +2.0 V The exposed pad must be soldered to the ground plane for PD[5:0]± to DRGND −0.3 V to DRVDD + 0.2 V the LFCSP package. Soldering the exposed pad to the PCB PCLK± to DRGND −0.3 V to DRVDD + 0.2 V increases the reliability of the solder joints, maximizing the PDOR± to DRGND −0.3 V to DRVDD + 0.2 V thermal capability of the package. FULL to DRGND −0.3 V to DRVDD + 0.2 V CLK± to AGND −0.3 V to AVDD + 0.2 V
Table 7.
FILL± to AGND −0.3 V to DRVDD + 0.2 V
Package Type θJA θJC Unit
DUMP to AGND −0.3 V to DRVDD + 0.2 V 56-Lead LFCSP_VQ (CP-56-1) 23.7 1.7 °C/W EMPTY to AGND −0.3 V to DRVDD + 0.2 V Typical θJA and θJC are specified for a 4-layer board in still air. VIN± to AGND −0.3 V to AVDD + 0.2 V Airflow increases heat dissipation, effectively reducing θJA. In VREF to AGND −0.3 V to AVDD + 0.2 V addition, metal in direct contact with the package leads from CML to AGND −0.3 V to AVDD + 0.2 V metal traces, through holes, ground, and power planes reduces CSB to DRGND −0.3 V to SPI_VDDIO + 0.3 V the θJA. SP_SCLK, SP_SDFS to AGND −0.3 V to SPI_VDDIO + 0.3 V SDIO to DRGND −0.3 V to SPI_VDDIO + 0.3 V SP_SDO to DRGND −0.3 V to SPI_VDDIO + 0.3 V
ESD CAUTION
Environmental Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature 300°C (Soldering, 10 sec) Junction Temperature 150°C Rev. 0 | Page 10 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS SPI TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS SPI REGISTER MAP THEORY OF OPERATION FIFO OPERATION Single Capture Mode Fill Pin Timing Dump Pin Timing SPORT Master Mode (Single Capture) Fill Pulse (1) Empty Signal (2) Full Signal (3) Dump Signal (4)—Transition to High SCLK Signal (5) SDFS Signal (6) Dump Signal (7)—Transition to Low Empty Signal (8)—Transition to High Parallel Master Mode (Single Capture) Fill Pulse (1) Empty Signal (2) Full Signal (3) Dump Signal (4)—Transition to High PCLK± Signal (5) PD[11:0] Signal (6) Dump Signal (7)—Transition to Low Empty Signal (8)—Transition to High Continuous Capture Mode FIFO OUTPUT INTERFACES SPORT Interface Serial Data Frame (Serial Bus Master) CMOS Output Interface LVDS Output Interface ANALOG INPUT AND VOLTAGE REFERENCE VREF CONFIGURATION USING THE SPI OUTLINE DIMENSIONS ORDERING GUIDE