Datasheet AD9271 (Analog Devices) - 4

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AD9271 SPECIFICATIONS AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 1.0 V internal ADC reference, fIN = 5 MHz, RS = 50 Ω, LNA gain = 15.6 dB (6), AAF LPF cutoff = 1/3 × fS, HPF cutoff = 700 kHz, full temperature, unless otherwise noted.
Table 1. AD9271-25 AD9271-40 AD9271-50 Parameter1 Conditions Min Typ Max Min Typ Max Min Typ Max Unit
LNA CHARACTERISTICS Gain = 5/6/8 Single-ended input 14/15.6/18 14/15.6/18 14/15.6/18 dB to differential output Single-ended input 8/9.6/12 8/9.6/12 8/9.6/12 dB to single-ended output Input Voltage Range, LNA output limited 400/333/250 400/333/250 400/333/250 mV p-p Gain = 5/6/8 to 2 V p-p differential SE2 output Input Common 1.4 1.4 1.4 V Mode Input Resistance RFB = 200 Ω 50 50 50 Ω RFB = 400 Ω 100 100 100 Ω RFB = ∞ 15 15 15 kΩ Input Capacitance LI-x 15 15 15 pF −3 dB Bandwidth 40 60 70 MHz Input Noise Current, 1.1 1.1 1.1 pA/√Hz Gain = 5/6/8 Input Noise Voltage, RS = 0 Ω, RFB = ∞ 1.4/1.4/1.3 1.3/1.2/1.1 1.3/1.2/1.1 nV/√Hz Gain = 5/6/8 1 dB Input VGAIN = 0 V 770/650/495 770/650/495 770/650/495 mV p-p Compression Point, Gain = 5/6/8 Noise Figure Active Termination RS = 50 Ω, RFB = 200 Ω 6.7 6.7 6.7 dB Match Unterminated RFB = ∞ 4.9 4.4 4.2 dB FULL-CHANNEL (TGC) CHARACTERISTICS AAF High-Pass Cutoff −3 dB DC/350/700 DC/350/700 DC/350/700 kHz AAF Low-Pass Cutoff −3 dB, programmable 1/3 × fSAMPLE 1/3 × fSAMPLE 1/3 × fSAMPLE MHz (8 to 18) (8 to 18) (8 to 18) Bandwidth Tolerance ±15 ±15 ±15 % Group Delay Variation f = 1 to 18 MHz, ±2 ±2 ±2 ns gain = 0 V to 1 V Input-Referred Noise LNA gain = 5/6/8, 1.7/1.6/1.5 1.6/1.4/1.3 1.6/1.4/1.2 nV/√Hz Voltage RFB = ∞ Correlated Noise Ratio No signal, correlated/ −30 −30 −30 dB uncorrelated Output Offset AAF high pass = −50 +50 −35 +35 −35 +35 LSB 700 kHz Signal-to-Noise Ratio (SNR) fIN = 5 MHz VGAIN = 0 V 65.8 64.4 63.7 dBFS at −7 dBFS fIN = 5 MHz VGAIN = 1 V 62 59.7 59 dBFS at −1 dBFS Rev. B | Page 4 of 60 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Crosspoint Switch TGC OPERATION Variable Gain Amplifier Gain Control VGA Noise Antialiasing Filter ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS QUICK START PROCEDURE SCHEMATICS AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE