Datasheet ADL5202 (Analog Devices) - 2
| Manufacturer | Analog Devices |
| Description | Wide Dynamic Range, High Speed, Digitally Controlled VGA |
| Pages / Page | 29 / 2 — ADL5202. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 1/2017—Rev. C … |
| Revision | D |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
ADL5202. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 1/2017—Rev. C to Rev. D. 9/2013—Rev. A to Rev. B. 1/2015—Rev. B to Rev. C
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ADL5202 Data Sheet TABLE OF CONTENTS
Features .. 1 Gain Up/Down Interface ... 16 Applications ... 1 Truth Table .. 17 Functional Block Diagram .. 1 Logic Timing ... 17 General Description ... 1 Circuit Description... 18 Revision History ... 2 Basic Structure .. 18 Specifications ... 3 Applications Information .. 19 Absolute Maximum Ratings .. 5 Basic Connections .. 19 ESD Caution .. 5 ADC Driving ... 19 Pin Configuration and Function Descriptions ... 6 Layout Considerations ... 21 Typical Performance Characteristics ... 8 Evaluation Board .. 22 Characterization and Test Circuits ... 15 Evaluation Board Control Software ... 22 Theory of Operation .. 16 Evaluation Board Schematics and Artwork .. 23 Digital Interface Overview .. 16 Evaluation Board Configuration Options ... 27 Parallel Digital Interface .. 16 Outline Dimensions ... 29 Serial Peripheral Interface (SPI) ... 16 Ordering Guide .. 29
REVISION HISTORY 1/2017—Rev. C to Rev. D 9/2013—Rev. A to Rev. B
Change to Features Section and General Description Section .. 1 Changed Logic Pins Absolute Maximum Rating from 3.6 V to Changes to Noise/Harmonic Performance Parameter, Table 1 ... 4 −0.3 V to +3.6 V (not to exceed |VPOS − 0.5 V| at any time) .. 5
1/2015—Rev. B to Rev. C 12/2012—Rev. 0 to Rev. A
Changes to Table 1 .. 4 Changes to Layout Consideration Section .. 21 Change to Table 3 ... 6
10/2011—Revision 0: Initial Version
Rev. D | Page 2 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION AND TEST CIRCUITS THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW PARALLEL DIGITAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) Fast Attack GAIN UP/DOWN INTERFACE TRUTH TABLE LOGIC TIMING CIRCUIT DESCRIPTION BASIC STRUCTURE Input System Output Amplifier Gain Control APPLICATIONS INFORMATION BASIC CONNECTIONS ADC DRIVING LAYOUT CONSIDERATIONS EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE EVALUATION BOARD SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS Configuration Options for the Main Section Configuration Options for the USB Section OUTLINE DIMENSIONS ORDERING GUIDE
ADL5202 Data Sheet TABLE OF CONTENTS
Features .. 1 Gain Up/Down Interface ... 16 Applications ... 1 Truth Table .. 17 Functional Block Diagram .. 1 Logic Timing ... 17 General Description ... 1 Circuit Description... 18 Revision History ... 2 Basic Structure .. 18 Specifications ... 3 Applications Information .. 19 Absolute Maximum Ratings .. 5 Basic Connections .. 19 ESD Caution .. 5 ADC Driving ... 19 Pin Configuration and Function Descriptions ... 6 Layout Considerations ... 21 Typical Performance Characteristics ... 8 Evaluation Board .. 22 Characterization and Test Circuits ... 15 Evaluation Board Control Software ... 22 Theory of Operation .. 16 Evaluation Board Schematics and Artwork .. 23 Digital Interface Overview .. 16 Evaluation Board Configuration Options ... 27 Parallel Digital Interface .. 16 Outline Dimensions ... 29 Serial Peripheral Interface (SPI) ... 16 Ordering Guide .. 29
REVISION HISTORY 1/2017—Rev. C to Rev. D 9/2013—Rev. A to Rev. B
Change to Features Section and General Description Section .. 1 Changed Logic Pins Absolute Maximum Rating from 3.6 V to Changes to Noise/Harmonic Performance Parameter, Table 1 ... 4 −0.3 V to +3.6 V (not to exceed |VPOS − 0.5 V| at any time) .. 5
1/2015—Rev. B to Rev. C 12/2012—Rev. 0 to Rev. A
Changes to Table 1 .. 4 Changes to Layout Consideration Section .. 21 Change to Table 3 ... 6
10/2011—Revision 0: Initial Version
Rev. D | Page 2 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION AND TEST CIRCUITS THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW PARALLEL DIGITAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) Fast Attack GAIN UP/DOWN INTERFACE TRUTH TABLE LOGIC TIMING CIRCUIT DESCRIPTION BASIC STRUCTURE Input System Output Amplifier Gain Control APPLICATIONS INFORMATION BASIC CONNECTIONS ADC DRIVING LAYOUT CONSIDERATIONS EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE EVALUATION BOARD SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS Configuration Options for the Main Section Configuration Options for the USB Section OUTLINE DIMENSIONS ORDERING GUIDE
