Datasheet ADL5336 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Cascadable IF VGAs with Programmable RMS Detectors |
| Pages / Page | 30 / 4 — ADL5336. Data Sheet. Parameter. Test Conditions/Comments. Min. Typ. Max. … |
| Revision | C |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
ADL5336. Data Sheet. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit
Model Line for this Datasheet
Text Version of Document
ADL5336 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
f = 350 MHz Noise Figure VGA1, Gain Code 00, VGAIN = 1 V 8 dB VGA2, Gain Code 11, VGAIN = 1 V 7.7 dB Output IP3 VGA1, Gain Code 00, VGAIN = 1 V 12 (19) dBV (dBm) Output Voltage Level of 1.0 V p-p VGA1, Gain Code 11, VGAIN = 1 V 10.5 (17.5) dBV (dBm) VGA2, Gain Code 00, VGAIN = 1 V 18 (28) dBV (dBm) VGA2, Gain Code 11, VGAIN = 1 V 16 (26) dBV (dBm) Output P1dB VGA1, Gain Code 00, VGAIN = 1 V 0 (7) dBV (dBm) VGA1, Gain Code 11, VGAIN = 1 V 0 (7) dBV (dBm) VGA2, Gain Code 00, VGAIN = 1 V −1.5 (+8.5) dBV (dBm) VGA2, Gain Code 11, VGAIN = 1 V −1.5 (+8.5) dBV (dBm) SQUARE LAW DETECTORS DTO1, DTO2 Output Setpoint SPI controlled, 3 dB steps −24 −3 dBV Output Range 0.1 VS/2 V AGC Step Response Range 5 dB input step, CAGC = 0.1 µF 1.5 ms DIGITAL LOGIC LE, CLK, DATA, SDO Input High Voltage, VINH >2.2 V Input Low Voltage, VINL <1.8 V Input Current, IINH/IINL <1 µA Input Capacitance, CIN 2 pF SPI TIMING LE, CLK, DATA, SDO fCLK 20 MHz tDH DATA hold time 5 ns tDS DATA setup time 5 ns tLH LE hold time 5 ns tLS LE setup time 5 ns tPW CLK high pulse width 5 ns tD CLK-to-SDO delay 5 ns POWER AND ENABLE VPOS, VPSD, COM, COMD, ENBL Supply Voltage Range 4.5 5 5.5 V Total Supply Current ENBL = 5 V 80 mA Disable Current ENBL = 0 V 4 mA Disable Threshold 2.3 V Enable Response Time Delay following low-to-high transition until 800 ns device meets full specifications in VGA mode Disable Response Time Delay following high-to-low transition until 20 ns device produces full attenuation in VGA mode Rev. C | Page 4 of 30 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CIRCUIT DESCRIPTION GAIN CONTROL INTERFACE INPUT AND OUTPUT IMPEDANCES AGC OPERATION REGISTER MAP AND CODES APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DETECTOR OUTPUT AND GAIN PIN COMMON-MODE BYPASSING SERIAL PORT CONNECTIONS MODE AND ENABLE CONNECTIONS ERROR VECTOR MAGNITUDE (EVM) EFFECT OF CAGC ON EVM AGC INSENSITIVITY TO MODULATION TYPE EFFECT OF SETPOINT ON EVM CASCADED VGA/AGC PERFORMANCE EVALUATION BOARD LAYOUT BILL OF MATERIALS (BOM) EVALUATION BOARD CONTROL SOFTWARE OUTLINE DIMENSIONS ORDERING GUIDE
f = 350 MHz Noise Figure VGA1, Gain Code 00, VGAIN = 1 V 8 dB VGA2, Gain Code 11, VGAIN = 1 V 7.7 dB Output IP3 VGA1, Gain Code 00, VGAIN = 1 V 12 (19) dBV (dBm) Output Voltage Level of 1.0 V p-p VGA1, Gain Code 11, VGAIN = 1 V 10.5 (17.5) dBV (dBm) VGA2, Gain Code 00, VGAIN = 1 V 18 (28) dBV (dBm) VGA2, Gain Code 11, VGAIN = 1 V 16 (26) dBV (dBm) Output P1dB VGA1, Gain Code 00, VGAIN = 1 V 0 (7) dBV (dBm) VGA1, Gain Code 11, VGAIN = 1 V 0 (7) dBV (dBm) VGA2, Gain Code 00, VGAIN = 1 V −1.5 (+8.5) dBV (dBm) VGA2, Gain Code 11, VGAIN = 1 V −1.5 (+8.5) dBV (dBm) SQUARE LAW DETECTORS DTO1, DTO2 Output Setpoint SPI controlled, 3 dB steps −24 −3 dBV Output Range 0.1 VS/2 V AGC Step Response Range 5 dB input step, CAGC = 0.1 µF 1.5 ms DIGITAL LOGIC LE, CLK, DATA, SDO Input High Voltage, VINH >2.2 V Input Low Voltage, VINL <1.8 V Input Current, IINH/IINL <1 µA Input Capacitance, CIN 2 pF SPI TIMING LE, CLK, DATA, SDO fCLK 20 MHz tDH DATA hold time 5 ns tDS DATA setup time 5 ns tLH LE hold time 5 ns tLS LE setup time 5 ns tPW CLK high pulse width 5 ns tD CLK-to-SDO delay 5 ns POWER AND ENABLE VPOS, VPSD, COM, COMD, ENBL Supply Voltage Range 4.5 5 5.5 V Total Supply Current ENBL = 5 V 80 mA Disable Current ENBL = 0 V 4 mA Disable Threshold 2.3 V Enable Response Time Delay following low-to-high transition until 800 ns device meets full specifications in VGA mode Disable Response Time Delay following high-to-low transition until 20 ns device produces full attenuation in VGA mode Rev. C | Page 4 of 30 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CIRCUIT DESCRIPTION GAIN CONTROL INTERFACE INPUT AND OUTPUT IMPEDANCES AGC OPERATION REGISTER MAP AND CODES APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DETECTOR OUTPUT AND GAIN PIN COMMON-MODE BYPASSING SERIAL PORT CONNECTIONS MODE AND ENABLE CONNECTIONS ERROR VECTOR MAGNITUDE (EVM) EFFECT OF CAGC ON EVM AGC INSENSITIVITY TO MODULATION TYPE EFFECT OF SETPOINT ON EVM CASCADED VGA/AGC PERFORMANCE EVALUATION BOARD LAYOUT BILL OF MATERIALS (BOM) EVALUATION BOARD CONTROL SOFTWARE OUTLINE DIMENSIONS ORDERING GUIDE
