Datasheet NCD2400M (IXYS) - 5

ManufacturerIXYS
DescriptionWide Capacitance Range, Non-volatileDigital Programmable Capacitor
Pages / Page22 / 5 — NCD2400M. 1.8 Digital Interface: Electrical Characteristics of SDA and …
File Format / SizePDF / 414 Kb
Document LanguageEnglish

NCD2400M. 1.8 Digital Interface: Electrical Characteristics of SDA and SCL. Parameter. Test Conditions. Symbol. Minimum. Typical

NCD2400M 1.8 Digital Interface: Electrical Characteristics of SDA and SCL Parameter Test Conditions Symbol Minimum Typical

Model Line for this Datasheet

Text Version of Document

INTEGRATED CIRCUITS DIVISION
NCD2400M 1.8 Digital Interface: Electrical Characteristics of SDA and SCL Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Input voltage Logic 1 threshold - VIH 0.75VDD - - Logic 0 threshold - VIL - - 0.25VDD V Hysteresis VIH - VIL VHYS 0.1 - - SDA Output voltage 1 Logic 1 10k pull-up resistor VOH 0.95VDD - - V Logic 0 IOL = 6mA VOL - - 0.4 Pull-up resistors, Internal TA=25°C 111 135 154 RPU k -40°C < TA < +105°C 88 135 186 Load capacitance - CLOAD 400 pF 1 SDA is an open drain pad. It is recommended to use a pull-up resistor with a value such that the current into pin SDA does not exceed 6mA, independent of the internal pull-up resistors.
1.9 Digital Interface: AC Characteristics Parameter Symbol Minimum Typical Maximum Unit
Serial clock (SCL) Frequency fSCL - - 400 kHz Duty cycle DSCL 40 - 60 % Rise / fal times tR / tF - - 100 ns Serial data (SDA) Setup time tsetup 300 - - ns Rise / fall times tR / tF - - 100 Data valid time1 tVD,DAT - - 180 ns Non-Volatile Write Programming time 2, 3 tPNV 4 8 ms 1 RP = 1k, CLOAD = 100pF 2 Programming time begins with the falling edge of CLK just after the CONFIG 0 ACK and ends with the rising Stop bit edge on SDA. 3 This time is for each non-volatile write commands, not the sum of all three commands.
S Chip ID + W A CONFIG 1 A CONFIG 0 A WAIT A WAIT A ... WAIT A P
Programming Time t t t R F setup SDA SCL Stable Data Line SDA tVD,DAT Valid Data Transitions Allowed Note: SDA output transitions occur only when SCL is low, as shown in the following timing diagram.
1.10 Power Supply Parameter Symbol Minimum Typical Maximum Unit
Supply voltage VDD 2.5 3.3 5.5 V Supply current IDD - 50 90 A R01
www.ixysic.com
5 Document Outline Features Applications Description 1. Specifications 1.1 Package Pinout 1.2 Pin Descriptions 1.3 Absolute Maximum Ratings 1.4 Recommended Operating Conditions 1.5 ESD Rating 1.6 General Conditions for Electrical Characteristics 1.7 Capacitor Electrical Characteristics 1.8 Digital Interface: Electrical Characteristics of SDA and SCL 1.9 Digital Interface: AC Characteristics 1.10 Power Supply 2. Performance Data 3. Functional Description 3.1 Introduction 3.2 Capacitive Digital to Analog Converter (CDAC) 3.3 Non-Volatile Memory Configuration 3.4 Device Address 3.5 Operating Modes 3.5.1 Volatile Mode 3.5.2 Non-Volatile Mode 3.6 I2C Serial Interface 3.6.1 Write Commands 3.6.2 Write Volatile Register Operation 3.6.3 Write Non-Volatile Memory Operation 3.6.4 Read Operation 3.6.5 Set Non-Volatile Mode Operation 3.6.6 Electrical and Timing Considerations 3.6.7 Application Diagrams 3.7 Capacitor Interface Electrical and Biasing Considerations 4. Capacitance Determination and Programming Procedure 5. Manufacturing Information 5.1 Moisture Sensitivity 5.2 ESD Sensitivity 5.3 Soldering Profile 5.4 Board Wash 5.5 Mechanical Dimensions 5.5.1 Package Dimensions 5.5.2 Tape & Reel Specification